參數(shù)資料
型號(hào): ZPSD503B1-90J
英文描述: Fast Recovery Glass Passivated Rectifier Diodes
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 130/153頁
文件大?。?/td> 1036K
代理商: ZPSD503B1-90J
PSD5XX Famly
127
-20
-25
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
IVIV
Interrupt Request Input to
Interrupt Output
(Note 3)
70
120
0
ns
t
RXIX
Read Vector to Interrupt
Request Clear
60
100
0
ns
t
ILIL
Interrupt Request Minimum
Pulse Width
40
45
0
ns
t
RLQV
RD to Data Valid Interrupt
Controller
(Note 1)
50
90
0
ns
-20
-25
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
f
MAX
t
CHCL
t
CLCH
t
CHPV
t
CHPV1
Maximum Frequency
20.00
12.50
0
MHz
Clock High Time
Clock Low Time
Clock to Output Delay
16
16
22
22
0
0
0
ns
ns
ns
50
55
Clock to Watchdog Output Delay
90
100
Add 20
ns
t
LVCH
Input Setup Time Relative
to Rising Level Clock
Add 20
(Note 2)
Any Input
45
60
ns
t
MIN
Minimum Clock Period
1/f
MAX
50
80
0
ns
NOTES:
1. Read to Data Valid of the Interrupt Request Latch and Interrupt Priority Status. RD timing has the same timing as PSEN, DS, LDS,
UDS signals.
2. For inputs which use PPLD only.
3. This timing is only valid when read to the interrupt request latch and priority status latch are not valid.
*
If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
Counter/Timer Timng
(3.0 V ± 10%)
Interrupt Timng
(3.0 V ± 10%)
AC/DC Parameters – ZPLDTimng Parameters
(ZPSD5XXV Versions)
相關(guān)PDF資料
PDF描述
ZPSD503B1-90JI Fast Recovery Glass Passivated Rectifier Diodes
ZPSD503B1-90LI Field-Programmable Peripheral
ZPSD503B1-90LM Field-Programmable Peripheral
ZPSD503B1-90U Field-Programmable Peripheral
ZPSD503B1-90UI Field-Programmable Peripheral
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