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參數(shù)資料
| 型號(hào)： | ZPSD503B1-20UI |
| 英文描述： | Fast Recovery Glass Passivated Rectifier Diodes |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 61/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD503B1-20UI |
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PSD5XX Famly
58
The PSD5XX provides many power saving options. By configuring the PMMRs (Power
Management Mode Registers), the user can reduce power consumption. Table 17 shows
the bit configuration of the PMMR0 and PMMR1. The microcontroller is able to control the
power consumption by changing the PMMR bits at run time.
9.5.1 Standby Mode
There are two Standby Modes in the PSD5XX:
J
Power Down Mode
J
Sleep Mode
9.5.2 Power Down
In this mode, the internal devices are shut down except for the I/O ports. There are three
ways the PSD5XX can enter into the Power Down Mode: by controlling the CSI input,
by activating the Automatic Power Down (APD) Logic, or when none of the inputs are
changing and the turbo bit is off.
J
The CSI
The CSI input pin is an active low signal. When low, the signal selects and enables the
PSD5XX. The PSD5XX enters into Power Down Mode immediately when the signal
turns high. This signal can be controlled by the microcontroller, external logic or it can
be grounded.
The CSI turns off the internal bus buffers in standby mode. The address and control
signals from the microcontroller are blocked from entering the ZPLD as inputs.
J
The APDLogic
The APD unit enables the user to enter a power down mode independent of controlling
the CSI input. This feature eliminates the need for external logic (decoders and latches)
to power down the PSD. The APD unit concept is based on tracking the activity on the
ALE pin. If the APD unit is enabled and ALE is not active, the 4-bit APD counter starts
counting and will overflow after 15 clocks, generating a PD (Power Down) signal
powering down the PSD. If sleep mode is enabled, then PD signal will also activate the
sleep mode. Immediately after ALE starts pulsing the PSD will get out of the power
down or sleep mode.
The operation of APD is controlled by the PMMR (see Figure 30a). PMMR1 bit 0 selects
the source of the APD counter clock. After reset the APD counter clock is connected to
PE7 (APD_CLK) on the PSD. In order to guarantee that the APD will not overflow there
should be less than 15 APD clocks between two ALE pulses. If CLKIN frequency is
adequate, then it can be connected to the APD and PE7 is used for other functions.
The next step is to select the ALE power down polarity. Usually, MCUs entering power
down will freeze their ALE at logic high or low. By programming bit 1 of PMMR0 the
power down polarity can be defined for the APD. If the APD detects that the ALE is
in the power down polarity for 15 APD counter clocks then the PSD will enter a power
down mode. To enable the APD operation, bit 2 in the PMMR0 should be set high.
9.5.3 Sleep Mode
The Sleep Mode is activated if the SLEEP EN bit, the APD EN bit, and the ALE Polarity bit
in the PMMR are set, and the APD Counter has overflowed after 15 clocks (see Figure 30).
In Sleep Mode the PSD5XX consumes less power than the Power Down Mode, with typical
I
CC
reduced to 10 μA (1 μA for ZPSD5XX devices).
In this mode, the Counter/Timers, the Interrupt Controller and the ZPLD still monitor their
inputs and respond to them. As soon as the ALE starts pulsing, the PSD5XX exits the
Sleep Mode.
The PSD access time from Sleep Mode is specified by t
LVDV1
. The ZPLD response time to
an input transition is specified by t
LVDV2
.
9.5
Power
Management
Unit
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