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參數(shù)資料
| 型號(hào)： | ZPSD502B1V-C-20U |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備 |
| 文件頁(yè)數(shù)： | 23/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD502B1V-C-20U |
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PSD5XX Famly
20
9.1.2.2 Port B Macrocell Structure
Figure 8 shows the PB Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port B. The two inputs, CLKIN and
MACRO-RST, are used as clock and clear inputs to all the macrocells. The CLKIN comes
directly from the CLKIN input pin. The MACRO-RST is the same as the Reset input pin
except it is user configurable.
The circuit of a PB Macrocell is shown in Figure 9. There are 10 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output,
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop.
J
Combinatorial Output
Select output from OR gate.
J
GPLD Input
Use Port B pin as dedicated input.
J
GPLD Output
Use Port B pin as dedicated output.
J
GPLD I/O
Use Port B pin as bidirectional pin.
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback
from the combinatorial output, to possibly expand the number of product terms
available to another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not
connected to a Port B pin, Port B can be configured to perform other user
defined I/O functions.
Each D flip flop in the macrocells has its own dedicated asynchronous clear, preset and
clock input. The signals are defined as follow:
J
PRESET
Active only if defined by a product term (PBx.PR)
J
CLEAR
Two selectable inputs: Reset input or user defined product term (PBx.RE)
J
CLK
Two selectable inputs – CLKIN input or user defined product term (PBx.CLK).
The macrocell is operated in Synchronous Mode if the clock input is CLKIN, and is in
Asynchronous Mode if the clock is a product-term clock defined by the user.
The PSD5XX
Architecture
(cont.)
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