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| 型號(hào)： | ZPSD502B1-90UI |
| 英文描述： | Avalanche Bridge Rectifiers |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 19/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD502B1-90UI |
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PSD5XX Famly
16
The PSD5XX
Architecture
(cont.)
9.1.2.1 Port A Macrocell Structure
Figure 6a shows the PA Macrocell block, which consists of 8 identical macrocells.
Each macrocell output can be connected to its own I/O pin on Port A. There are 3 user
programmable global product terms output from the GPLD’s AND ARRAY which are
shared by all the macrocells in Port A:
J
PA.OE
Enable or tri-state Port A output pins
J
PA.PR
Preset D flip flop in the macrocells
J
PA.RE
Reset/Clear D flip flop in the macrocells
Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip
flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as
the Reset input pin except it is user configurable.
The circuit of a Port A Macrocell is shown in Figure 7. There are 6 product terms from the
GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the output,
and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop
J
Combinatorial Output
Select output from OR gate
J
GPLD Input
Use Port A pin as dedicated input
J
GPLD Output
Use Port A pin as dedicated output
J
GPLD I/O
Use Port A pin as bidirectional pin
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback
from the combinatorial output, to expand the number of product terms available to
another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected to a
Port A pin, Port A can be configured to perform other user defined I/O functions.
The two global product terms assigned for asynchronous clear (PA.RE) and preset (PA.PR)
are mainly for proper Port A Macrocell initialization. The macrocell flip-flop can also be
cleared during reset by MACRO-RST, if such an option is chosen. The clock source is
always the input clock CLKIN.
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