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| 型號(hào)： | ZPSD502B1-15LI |
| 英文描述： | Avalanche Glass Passivated Bridge Rectifiers |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 87/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD502B1-15LI |
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PSD5XX Famly
84
9.6.2.2 Command Registers for Counter/Timers CMD0, CMD1, CMD2, CMD3:
Each of the Counter/Timer units (CTU) has one Command Register associated with it.
A description of these various CTU command bits is provided below. Refer to CSIOP
Tables 23 and 24 for their addresses and selection details. Figure 43 describes the
Command Register bits.
The following is the description of Counter/Timer0 CMD0 register bits. Bits in CMD1, CMD2
and CMD3 have similar descriptions. Refer to Figure 43 also.
Counter/Timer
Registers
(Cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Enable/
Disable
Using
Pin,
PPLD
Macrocell
or
Software
Software
Gating
Bit for
Load/
Store cmd
Using Pin
or PPLD
Macrocell
Pin/
PPLD
Macrocell
Input
Polarity
Output
Polarity
Select
Counter
Increment/
Decrement
Mode
Select
NOTES:
1. At RESET these bits come up as 0s.
2. In WatchDog Mode, CMD2 register bits are Don’t Cares.
Mode Select Bit (0):
This bit selects the Counter/Timer0 operation mode. After
RESET Counter/Timer0 initializes in waveform/event count
mode. When this bit is set to
1: The Counter/Timer0 operates in Pulse/Time capture
modes.
0: The Counter/Timer0 operates in Waveform/Event count
modes.
NOTE:
See Table 24 for details of Timer mode set up.
Increment/Decrement Bit (1):
This bit is used to set the Counter/Timer in increment or
decrement mode. The RESET state is Decrement mode.
When this bit is set to
1: The Counter/Timer0 is in increment mode.
0: The Counter/Timer0 is in decrement mode.
NOTE:
In WatchDog mode Counter #2 is in decrement
mode only.
Select Counter Bit (2):
This bit is used to select or deselect Counter/Timer0.
At RESET this bit initializes as 0 which means
Counter/Timer0 is deselected. When this bit is set to
1: Counter/Timer0 is selected (counting enabled).
0: Counter/Timer0 is deselected (counting disabled).
After a Counter/Timer is started by the Global Command Register, it can be re-configured by
changing the individual Command Register. The steps to re-configure a Counter/Timer are:
1. Disable the Counter/Timer by writing a “0” to the Select Counter Bit (bit 2) of the
Command Register.
2. Change the Counter/Timer configuration by writing the new value (bit 2 remains at “0”)
to the Command Register.
3. Enable the Counter/Timer again by writing the new value with bit 2 set to “1” to the
Command Register.
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