參數(shù)資料
型號(hào): ZPSD413A2
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備(可編程邏輯,零功耗,16K的位的SRAM,40余個(gè)可編程輸入/輸出,通用PLD的有59個(gè)輸入)
文件頁數(shù): 65/108頁
文件大?。?/td> 626K
代理商: ZPSD413A2
ZPSD4XX Famly
5-65
The Peripheral I/O Mode is one of the operating modes of Port A. In this mode, Port A
is connected to the data bus of peripheral devices. Port A is enabled only when
the microcontroller is accessing the devices, otherwise the Port is tri-stated. This feature
enables the microcontroller to access external devices without requiring buffers and
decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode.
The memory address space occupied by the devices are defined by two signals: PSEL0 and
PSEL1. The signals are direct outputs from the Decoding PLD (DPLD). Whenever any of
the signals is active, the Port A driver is enabled, and the direction of the data flow is deter-
mined by the RD/WR signals.
The Peripheral I/O Mode and the peripheral select signals are configured and defined in the
PSDsoft Software (see the section on I/O Port for configuration). The PIO bit in the VM
Register (see Table 17) also needs to be set to “1” by the user to initialize the Peripheral I/O
Mode.
The Peripheral I/O mode can be used, for example, in DMA applications where the
microcontroller does not support DMA operations, such as tri-stating the address/data bus.
Figure 35 shows a block diagram of a microcontroller and ZPSD4XX based design that
makes use of this mode. In this application, the microcontroller has a multiplexed bus which
is connected to the ADIO port. The C and D ports connect to the peripheral address bus
and are both configured in Address Out Mode. Port A is configured in the Peripheral I/O
mode and is connected to the peripheral data bus. Ports B and E are used to generate
control signals.
During normal activity, the microcontroller has access to any peripheral (memory or I/O
device) through the ZPSD4XX device. When there is a DMA request, the
microcontroller tri-states the address bus on Ports C and D by writing a “0” to the port
Direction Registers. The DMA controller then takes over the data and address buses after
receiving acknowledgement from the microcontroller.
Peripheral
I/O
Figure 34. Port A In Peripheral I/OMode
RD
PSEL0
PSEL1
D0 – D7
WR
PA0 – PA7
相關(guān)PDF資料
PDF描述
ZPSD502B1 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
ZPSD502B1V Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
ZPSD512B1 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
ZPSD512B1V Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
ZPSD513B1 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD413A2-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD413A2-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD413A2-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD413A2-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD413A2-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral