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參數(shù)資料
| 型號： | ZPSD412A2-20UI |
| 英文描述： | Silicon Bridge Rectifiers |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 8/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | ZPSD412A2-20UI |
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PSD4XX Famly
5
5.0
Integrated
Power
Management
TM
Operation
Upon each address or logic input change to the ZPSD, the device powers up from low
power standby for a short time. Then the ZPSD consumes only the necessary power to
deliver new logic or memory data to its outputs as a response to the input change. After the
new outputs are stable, the ZPSD latches them and automatically reverts back to standby
mode. The I
CC
current flowing during standby mode and during DC operation is identical
and is only a few microamperes.
The ZPSD automatically reduces its DC current drain to these low levels and does not
require controlling by the CSI (Chip Select Input). Disabling the CSI pin unconditionally
forces the ZPSD to standby mode independent of other input transitions.
The only significant power consumption in the ZPSD occurs during AC operation.
The ZPSD contains the first architecture to apply zero power techniques to memory and
logic blocks.
Figure 2 compares ZPSD Zero-power operation to the operation of a discrete solution.
A standard microcontroller (MCU) bus cycle usually starts with an ALE (or AS) pulse and
the generation of an address. The ZPSD detects the address transition and powers up for a
short time. The ZPSD then latches the outputs of the PAD, EPROM and SRAM to the new
values. After finishing these operations, the ZPSD shuts off its internal power, entering
standby mode. The time taken for the entire cycle is less than the ZPSD’s “access time.”
The ZPSD will stay in standby mode if inputs do not change between bus cycles. In an
alternate system implementation using discrete EPROM, SRAM, and other discrete
components, the system will consume operating power during the entire bus cycle. This is
because the chip select inputs on the memory devices are usually active throughout the
entire cycle. The AC power consumption of the ZPLD may be calculated using the
composite frequency of the MCU address and control signals, as well as any other logic
inputs to the ZPLD.
NOTE:
The ZPSD4XX is rated for lower standby current (I
SB
) than the PSD4XX.
ALE
DISCRETE EPROM, SRAM & LOGIC
ADDRESS
EPROM
ACCESS
SRAM
ACCESS
EPROM
ACCESS
I
CC
ZPSD
ZPSD
ZPSD
TIME
Figure 2. Zero-Power Operation vs. Dscrete Implementation
相關PDF資料 |
PDF描述 |
|---|---|
| ZPSD412A2-70J | Field-Programmable Peripheral |
| ZPSD412A2-70JI | Field-Programmable Peripheral |
| ZPSD412A2-70LI | Field-Programmable Peripheral |
| ZPSD412A2-70U | Field-Programmable Peripheral |
| ZPSD412A2-70UI | Field-Programmable Peripheral |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD412A2-70J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD412A2-70JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD412A2-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD412A2-70U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| ZPSD412A2-70UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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