參數(shù)資料
型號(hào)： ZPSD302
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入）
文件頁(yè)數(shù)： 28/90頁(yè)
文件大?。?/td> 491K
代理商： ZPSD302
EPROM
The EPROM power consumption in the PSD is controlled by bit 3 in the PMMR0 – EPROM
CMiser. Upon reset the CMiser bit is OFF. This will cause the EPROM to be ON at all times
as long as CSI is enabled (low). The reason this mode is provided is to reduce the access
time of the EPROM by 10 ns relative to the low power condition when CMiser is ON.
If CSI is disabled (high) the EPROM will be deselected and will enter standby mode (OFF)
overriding the state of the CMiser.
If CMiser is set (ON) then the EPROM will enter the standby mode when not selected.
This condition can take place when CSI is high or when CSI is low and the EPROM is not
accessed. For example, if the MCU is accessing the SRAM, the EPROM will be
deselected and will be in low power mode.
An additional advantage of the CMiser is achieved when the PSD is configured in the by 8
mode (8 bit data bus). In this case an additional power savings is achieved in the EPROM
(and also in the SRAM) by turning off 1/2 of the array even when the EPROM is accessed
(the array is divided internally into odd and even arrays).
The power consumption for the different EPROM modes is given in the DC Characteristics
table under I
CC
(DC) EPROM Adder.
A19/CSI
When configured as CSI, a high on this pin deselects and powers down the chip. A low on
this pin puts the chip in normal operational mode. When CSI is enabled and none of the
inputs are changing, the ZPSD is in power-down mode (Turbo Bit = OFF). For ZPSD3XX
states during the power-down mode, see Tables 12 and 13, and Figure 13.
In A19 mode, the pin is an additional input to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a general-purpose logic input (CADLOG3 = 0). A19 can be
configured as ALE dependent or as a transparent input (see Table 8). In this mode, the chip
is always enabled.
ZPSD3XX Famly
3-28
Power
Management
The power consumption of ZPSD is controlled by the A19/CSI input pin and two power
management bits:
J
Turbo Bit
J
CMiser Bit
Turbo Bit
The Turbo bit is an “on the fly” configurable volatile bit. This bit enables the MCU to
control the PAD power consumption and propagation delay. When Turbo is OFF
(Logic “1”), the PAD is in Zero Power Mode and the PAD propagation delay is slower (see
parameter tables). The EPROM or SRAM access time is not affected. When the Turbo bit is
ON (Logic “0”), the Zero Power option of the PAD is disabled placing the PAD in high speed
mode. The Turbo bit is located in the Power Management Register at address CSIOP +
displacement of 10 H at data bus bit zero. Upon reset the Turbo bit is ON.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
*
Turbo
Bit
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = OFF
1 = OFF
Power Management Register (PMR)
*
Future Configuration bits are reserved and should be set to one.
相關(guān)PDF資料
PDF描述
ZPSD302V Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
ZPSD413A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD401A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
ZPSD401A2 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有59個(gè)輸入)
ZPSD403A1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個(gè)可編程I/O,通用PLD有37個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD302-15LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD302-15LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD302-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD302-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD302-70LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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