參數(shù)資料
型號(hào): ZL50119
廠商: Zarlink Semiconductor Inc.
英文描述: 32, 64 and 128 Channel CESoP Processors
中文描述: 32,64和128頻道CESoP處理器
文件頁(yè)數(shù): 68/95頁(yè)
文件大小: 1157K
代理商: ZL50119
ZL50115/16/17/18/19/20
Data Sheet
68
Zarlink Semiconductor Inc.
12.0 AC Characteristics
12.1 TDM Interface Timing - ST-BUS
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device
sourcing the data, or Master mode, where the TDM clocks are generated from the ZL5011x.
12.1.1 ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification
Data Format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-BUS
8.192 Mbps
mode
TDM_CLKi Period
t
C16IP
t
C16IH
t
C16IL
t
C4IP
t
C4IH
t
C4IL
t
FOIW
54
60
66
ns
TDM_CLKi High
27
-
33
ns
TDM_CLKi Low
27
-
33
ns
ST-BUS
2.048 Mbps
mode
TDM_CLKi Period
-
244.1
-
ns
TDM_CLKi High
110
-
134
ns
TDM_CLKi Low
110
-
134
ns
All Modes
TDM_F0i Width
8.192 Mbps
2.048 Mbps
50
200
-
-
-
300
ns
TDM_F0i Setup Time
t
FOIS
5
-
-
ns
With respect to
TDM_CLKi
falling edge
TDM_F0i Hold Time
t
FOIH
5
-
-
ns
With respect to
TDM_CLKi
falling edge
TDM_STo Delay
t
STOD
1
-
20
ns
With respect to
TDM_CLKi
Load C
L
= 50 pF
With respect to
TDM_CLKi
TDM_STi Setup Time
t
STIS
5
-
-
ns
TDM_STi Hold Time
t
STIH
5
-
-
ns
With respect to
TDM_CLKi
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