參數(shù)資料
型號: ZL30415GGC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH Clock Multiplier PLL
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA64
封裝: 8 X 8 MM, 0.80 MM PITCH, CABGA-64
文件頁數(shù): 16/23頁
文件大?。?/td> 347K
代理商: ZL30415GGC
ZL30415
Data Sheet
16
Zarlink Semiconductor Inc.
AC Electrical Characteristics
- C19i Input to OC-CLKo Output Timing
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Typical figures are for design aid only: not guaranteed and not subject to production testing.
Figure 14 - C19i Input to OC-CLKo Output Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
C19i(CMOS) to C19o(LVPECL) delay
t
C19D
t
C38D
t
C77D
t
C155D
t
C622D
d
C
1.4
3.3
5.1
ns
2
C19i(CMOS) to OC-CLKo(38) delay
1.2
3.0
4.8
ns
3
C19i(CMOS) to OC-CLKo(77) delay
0.9
2.6
4.4
ns
4
C19i(CMOS) to OC-CLKo(155) delay
0.6
2.3
4.1
ns
5
C19i(CMOS) to OC-CLKo(622) delay
0
0.8
1.6
ns
6
All Output Clock duty cycle
48
50
52
%
OC-CLKo(38)
(38.88 MHz)
V
T-LVPECL
C19i
(19.44 MHz)
V
T-CMOS
t
C19D
OC-CLKo(19)
(19.44 MHz)
V
T-LVPECL
t
C38D
OC-CLKo(155)
(155.52 MHz)
V
T-LVPECL
OC-CLKo(77)
(77.76 MHz)
V
T-LVPECL
t
C77D
t
C155D
Note: All output clocks have nominal 50% duty cycle.
OC-CLKo(622)
(622.08 MHz)
V
T-LVPECL
t
C622D
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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