參數(shù)資料
型號(hào): ZL30121GGG2
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH Low Jitter System Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝: 9 X 9 MM, 0.80 MM PITCH, LEAD FREE, CABGA-100
文件頁數(shù): 26/30頁
文件大?。?/td> 326K
代理商: ZL30121GGG2
ZL30121
Data Sheet
26
Zarlink Semiconductor Inc.
56
sdh_fp0_freq
05
Control register to select the sdh_fp0 frame
pulse frequency
R/W
57
sdh_fp0_type
23
Control register to select fp0 type
R/W
58
sdh_fp0_fine_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59
sdh_fp0_fine_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A
sdh_fp0_coarse_offset
00
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
R/W
5B
sdh_fp1_freq
03
Control register to select sdh_fp1 frame pulse
frequency
R/W
5C
sdh_fp1_type
03
Control register to select fp1 type
R/W
5D
sdh_fp1_fine_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5E
sdh_fp1_fine_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5F
sdh_fp1_coarse_offset
00
Programmable frame pulse phase offset in
multiples of 8 kHz cycles
R/W
Differential Output Configuration
60
diff_ctrl
A3
Control register to enable diff0, diff1
R/W
61
diff_sel
53
Control register to select the diff0 and diff1
frequencies
R/W
External Feedback Configuration
62
fb_control
80
Control register to enable fb_clk and the FB
PLL, int/ext feedback select
R/W
63
fb_offset_fine
F5
Control register for the output/output phase
alignment fine tuning
R/W
64
reserved
N * 8 kHz Reference Control
65
ref_freq_mode_0
00
Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref3
R/W
66
ref_freq_mode_1
00
Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
R/W
67
custA_mult_0
00
Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
Table 5 - Register Map (continued)
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