參數(shù)資料
型號: ZL30119GGG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: SONET/SDH OC-48/OC-192 Line Card Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100
封裝: 9 X 9 MM, 0.80 MM PITCH, CABGA-100
文件頁數(shù): 12/28頁
文件大?。?/td> 514K
代理商: ZL30119GGG
ZL30119
Data Sheet
12
Zarlink Semiconductor Inc.
1.0 Functional Description
The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and
synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one
of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
1.1 DPLL Features
The ZL30119 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or
frame pulse synchronization. Table 1 lists the feature summary for both DPLLs.
Feature
DPLL1
DPLL2
Modes of Operation
Free-run, Normal (locked), Holdover
Free-run, Normal (locked), Holdover.
Loop Bandwidth
User selectable: 14 Hz, 28 Hz, or
wideband
1
(890 Hz / 56 Hz / 14 Hz)
1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or
greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the
loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz.
Fixed: 14 Hz
Phase Slope Limiting
User selectable: 885 ns/s, 7.5
μ
s/s,
61
μ
s/s, or unlimited
User selectable: 61
μ
s/s, or unlimited
Pull-in Range
Fixed: 130 ppm
Fixed: 130 ppm
Reference Inputs
Ref0 to Ref7
Ref0 to Ref7
Sync Inputs
Sync0, Sync1, Sync2
Sync inputs are not supported.
Input Ref Frequencies
2 kHz, N * 8 kHz up to 77.76 MHz
2 kHz, N * 8 kHz up to 77.76 MHz
Supported Sync Input
Frequencies
166.67 Hz, 400 Hz, 1 kHz, 2 kHz,
8 kHz, 64 kHz.
Sync inputs are not supported.
Input Reference
Selection/Switching
Automatic (based on programmable
priority and revertiveness), or manual
Automatic (based on programmable
priority and revertiveness), or manual
Hitless Ref Switching
Can be enabled or disabled
Can be enabled or disabled
Output Clocks
diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1,
p0_clk0, p0_clk1, p1_clk0, p1_clk1,
fb_clk.
p0_clk0, p0_clk1, p1_clk0, p1_clk1.
Output Frame Pulses
sdh_fp0, sdh_fp1, p0_fp0, p0_fp1
synchronized to active sync reference.
p0_fp0, p0_fp1 not aligned to sync
reference.
Supported Output Clock
Frequencies
As listed in Table 4
As listed in Table 4 for p0_clk0, p0_clk1,
p1_clk0, p1_clk1
Supported Output
Frame Pulse
Frequencies
As listed in Table 4
As listed in Table 4 for p0_fp0, p0_fp not
aligned to sync reference.
External Pins Status
Indicators
Lock, Holdover
None
Table 1 - DPLL1 and DPLL2 Features
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