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參數(shù)資料
| 型號： | ZL30119GGG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, 0.80 MM PITCH, LEAD FREE, CABGA-100 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大小： | 514K |
| 代理商： | ZL30119GGG2 |
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ZL30119
Data Sheet
23
Zarlink Semiconductor Inc.
4A
p1_freq_0
C1
Control register for the [7:0] bits of the N of
N*8k clk0
R/W
4B
p1_freq_1
00
Control register for the [13:8] bits of the N of
N*8k clk0
R/W
4C
p1_clk0_offset90
00
Control register for the p1_clk0 phase position
coarse tuning
R/W
4D
p1_clk1_div
3F
Control register for the p1_clk1 frequency
selection
R/W
4E
p1_clk1_offset90
00
Control register for the p1_clk1 phase position
coarse tuning
R/W
4F
p1_offset_fine
00
Control register for the output/output phase
alignrment fine tuning
R/W
SDH Configuration Registers
50
sdh_enable
8F
Control register to enable sdh_clk0, sdh_clk1,
sdh_fp0, sdh_fp1 and the SDH PLL
R/W
51
sdh_run
0F
Control register to generate sdh_clk0,
sdh_clk1, sdh_fp0 and sdh_fp1
R/W
52
sdh_clk_div
42
Control register for the sdh_clk0 and sdh_clk1
frequency selection
R/W
53
sdh_clk0_offset90
00
Control register for the sdh_clk0 phase position
coarse tuning
R/W
54
sdh_clk1_offset90
00
Control register for the sdh_clk1 phase position
coarse tuning
R/W
55
sdh_offset_fine
00
Control register for the output/output phase
alignrment fine tuning for sdh path
R/W
56
sdh_fp0_freq
05
Control register to select the sdh_fp0 frame
pulse frequency
R/W
57
sdh_fp0_type
23
Control register to select fp0 type
R/W
58
sdh_fp0_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
59
sdh_fp0_offset_1
00
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5A
sdh_fp0_offset_2
00
Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
5B
sdh_fp1_freq
03
Control register to select sdh_fp1 frame pulse
frequency
R/W
5C
sdh_fp1_type
03
Control register to select fp1 type
R/W
5D
sdh_fp1_offset_0
00
Bits [7:0] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
Type
Table 5 - Register Map (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30120 | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30120GGG | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30120GGG2 | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30121GGG2 | SONET/SDH Low Jitter System Synchronizer |
| ZL30121 | SONET/SDH Low Jitter System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30120 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30120GGG | 制造商:Microsemi Corporation 功能描述:T1/E1 SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA |
| ZL30120GGG2 | 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA |
| ZL30121 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH Low Jitter System Synchronizer |
| ZL30121GGG | 制造商:Microsemi Corporation 功能描述:SYS SYNCHRONIZER 100CABGA - Trays |
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