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參數(shù)資料
| 型號(hào)： | ZL30119 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| 中文描述： | SONET / SDH的OC-48/OC-192線路卡同步器 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 514K |
| 代理商： | ZL30119 |
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ZL30119
Data Sheet
8
Zarlink Semiconductor Inc.
J10
p1_clk0
O
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS).
This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
K10
p1_clk1
O
Programmable Synthesizer1 - Output Clock 1 (LVCMOS).
This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
H10
fb_clk
O
Feedback Clock (LVCMOS).
This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
E1
dpll2_ref
O
DPLL2 Selected Output Reference (LVCMOS).
This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
A9
B10
diff0_p
diff0_n
O
Differential Output Clock 0 (LVPECL).
This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 155.52 MHz.
A10
B9
diff1_p
diff1_n
O
Differential Output Clock 1 (LVPECL).
This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 622.08 MHz clock.
Control
H5
rst_b
I
Reset (LVCMOS, Schmitt Trigger).
A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
J5
dpll1_hs_en
I
u
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger).
A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pull up to Vdd.
C2
D2
dpll1_mod_sel0
dpll1_mod_sel1
I
u
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger).
During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the
dpll1_modesel
register
through the serial interface. This pin is internally pull up to Vdd.
K1
diff0_en
I
u
Differential Output 0 Enable (LVCMOS, Schmitt Trigger).
When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pull up to
Vdd.
D3
diff1_en
I
u
Differential Output 1 Enable (LVCMOS, Schmitt Trigger).
When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pull up to
Vdd.
Pin #
Name
I/O
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL30119_06 | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30119GGG | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30119GGG2 | SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30120 | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30120GGG | SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL30119_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH OC-48/OC-192 Line Card Synchronizer |
| ZL30119GGG | 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:Microsemi Corporation 功能描述:LOW JITTER LINECARD SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30119GGG2 | 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA |
| ZL30120 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer |
| ZL30120GGG | 制造商:Microsemi Corporation 功能描述:T1/E1 SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA |
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