參數(shù)資料
型號： ZL30119_06
廠商： Zarlink Semiconductor Inc.
英文描述： SONET/SDH OC-48/OC-192 Line Card Synchronizer
中文描述： SONET / SDH的OC-48/OC-192線路卡同步器
文件頁數(shù)： 9/28頁
文件大小： 514K
代理商： ZL30119_06
ZL30119
Data Sheet
9
Zarlink Semiconductor Inc.
Status
H1
dpll1_lock
O
Lock Indicator (LVCMOS).
This is the lock indicator pin for DPLL1. This output
goes high when DPLL1’s output is frequency and phase locked to the input
reference.
J1
dpll1_holdover
O
Holdover Indicator (LVCMOS).
This pin goes high when DPLL1 enters the
holdover mode.
Serial Interface
E2
sck
I
Clock for Serial Interface (LVCMOS).
Serial interface clock.
F1
si
I
Serial Interface Input (LVCMOS).
Serial interface data input pin.
G1
so
O
Serial Interface Output (LVCMOS).
Serial interface data output pin.
E3
cs_b
I
u
Chip Select for Serial Interface (LVCMOS).
Serial interface chip select. This
pin is internally pull up to Vdd.
G2
int_b
O
Interrupt Pin (LVCMOS).
Indicates a change of device status prompting the
processor to read the enabled interrupt service registers (ISR). This pin is an
open drain, active low and requires an external pull up to VDD.
APLL Loop Filter
A6
sdh_filter
A
External Analog PLL Loop Filter terminal.
B6
filter_ref0
A
Analog PLL External Loop Filter Reference.
C6
filter_ref1
A
Analog PLL External Loop Filter Reference.
JTAG and Test
J4
tdo
O
Test Serial Data Out (Output).
JTAG serial data is output on this pin on the
falling edge of tck. This pin is held in high impedance state when JTAG scan is
not enabled.
K2
tdi
I
u
Test Serial Data In (Input).
JTAG serial test instructions and data are shifted in
on this pin. This pin is internally pull up to Vdd. If this pin is not used then it
should be left unconnected.
H4
trst_b
I
u
Test Reset (LVCMOS).
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-
up to ensure that the device is in the normal functional state. This pin is internally
pulled up to Vdd. If this pin is not used then it should be connected to GND.
K3
tck
I
Test Clock (LVCMOS):
Provides the clock to the JTAG test logic. If this pin is not
used then it should be pulled down to GND.
J3
tms
I
u
Test Mode Select (LVCMOS).
JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Pin #
Name
I/O
Type
Description
相關(guān)PDF資料
PDF描述
ZL30119GGG SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30119GGG2 SONET/SDH OC-48/OC-192 Line Card Synchronizer
ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120GGG SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL30119GGG 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:Microsemi Corporation 功能描述:LOW JITTER LINECARD SYNCHRONIZER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30119GGG2 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SONET/SDH SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC SONET/SDH SYNCH 100CABGA
ZL30120 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
ZL30120GGG 制造商:Microsemi Corporation 功能描述:T1/E1 SYSTEM SYNCHRONIZER 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA
ZL30120GGG2 制造商:Microsemi Corporation 功能描述:LINE CARD SYNCHRONIZER 100CABGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC LINE CARD SYNCH 100CABGA 制造商:Microsemi Corporation 功能描述:IC LINE CARD SYNCH 100CABGA
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