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ZL20200
Data Sheet
24
Zarlink Semiconductor Inc.
The 4 registers address 0 to 3 are assigned as follows:
A feature of this programming approach is that once a phone operating mode has been selected and set up via the
serial bus, all power control can then be via the TX RXB, ENABLE1 and ENABLE2 control pins. Alternatively full
power control is possible via the 3 wire serial bus without the use of any external control pins.
If ENABLE1 and ENABLE2 are both low then the device is in Sleep mode. No circuits will be enabled unless either
ENABLE1 or ENABLE2 are high regardless of the contents of the receive and transmit registers.
An example of how these control bits can be used, is that the oscillators and PLL circuits can be powered up and
allowed to settle prior to powering up the complete transmit or receive path. In the case of the receive path the UHF
synthesizer, UHF LO input buffer, UHF LO Buffer and Receive VHF VCO, Receive VHF PLL bits would be set in the
ENABLE1 Configuration register. The ENABLE2 Configuration register would contain these bits plus the remainder
of the receive path bits, Receive IF input, Receive AGC amplifier, Receive quadrature down-converter and receive
baseband section.
This is demonstrated in the following examples.
2.1.1 Power Control Modes - TDMA (IS136)
In a TDMA system the transceiver will either operate in receive only, or transmit only mode. It is assumed that an
interim power on state will be used during which the oscillators and PLLs will be set up, and allowed to settle prior
to activating the full signal path. The suggested programming for the power control registers (0 - 3) is shown in the
table below.
Register
Address
Register
Name
Description
0
Receive
All circuit blocks required in receive mode should be set to 1. This register will be
selected when TX RXB is low. No circuits will be actually powered up if ENABLE1
and ENABLE 2 are both low.
1
Transmit
Transmit register All circuit blocks required in transmit mode should be set to 1. In
duplex modes e.g. AMPS then both receive and transmit circuits must be selected.
This register will be selected when TX RXB is high. No circuits will be actually
powered up if ENABLE1 and ENABLE 2 are both low
2
ENABLE1
Configuration
This register determines which circuit sections are powered up when ENABLE1 is
high. The contents of this register are logical ANDed with the contents of the
Receive or Transmit register as selected by TX RXB input.
3
ENABLE2
Configuration
This register determines which circuit sections are powered up when ENABLE2 is
high. The contents of this register are logical ANDed with the contents of the
Receive or Transmit register as selected by TX RXB input.
Table 6 - Power Control Register Functions
Bit
Circuit
Section
Receive
Addr 0
Transmit
Addr 1
Enable 1
Config.
Addr 2
Enable 2
Config.
Addr 3
Comments
23
Not used
0
0
0
0
22
Receive Baseband section
1
0
0
1
Table 7 - Programming for the Power Control Registers (0 - 3)