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參數(shù)資料
| 型號(hào)： | ZL10313UBH |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | WIRE, PTFE, A, WHITE, 7/.012MM, 100M; Area, conductor CSA:0.079mm2; Conductor make-up:7/0.12mm; Voltage rating, AC:300V; Current rating:3A; Colour, primary insulation:White; Material, primary insulation:PTFE; Diameter, RoHS Compliant: Yes |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 23/26頁 |
| 文件大小： | 450K |
| 代理商： | ZL10313UBH |
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ZL10313
Data Sheet
23
Zarlink Semiconductor Inc.
Note 1:
5 V tolerant pins with thresholds related to 3.3 V.
47
MOVAL
MPEG data output valid. High during the MOCLK
cycles when valid data bytes are being output.
O
CMOS
Tri-state
3.3
2
48,49,52
,53,56,
57,60,61
MDO[0:7]
MPEG transport packet data output bus. Can be tri-
stated under control of a register bit.
O
CMOS
Tri-state
3.3
2
62
MOCLK
MPEG clock output at the data byte rate.
O
CMOS
Tri-state
3.3
12
63
BKERR
Active low uncorrectable block indicator or no-signal
indicator. Mode selected by ERR_IND bit (#7) of the
MON_CTRL register. Can also be inverted.
O
CMOS
Tri-state
3.3
2
64
STATUS
Status output. Register defined function including
audio frequency proportional to BER (acts as input
only in production test modes)
I/O
CMOS
3.3
2
5, 39, 55
Vdd
Peripheral supply pins. All pins
must
be connected.
3.3
27
Vdd
Peripheral supply pin used for the ADC.
3.3
7, 12,
44, 50,
59
CVdd
Core supply pins. All pins
must
be connected.
1.8
17, 22,
32, 34
CVdd
PLL/ADC supply pins. All pins
must
be connected.
1.8
6, 8, 13,
40, 45
51, 54,
58
Gnd
Ground supply pins. All pins
must
be connected.
0
18, 21,
23 26,
28, 31,
33
Gnd
PLL/ADC ground supply pins. All pins
must
be
connected.
0
Pin Description Table
Pin
Name
Description
I/O
Note
V
mA
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