參數(shù)資料
型號(hào)： ZL10313
廠商： Zarlink Semiconductor Inc.
英文描述： Satellite Demodulator
中文描述： 衛(wèi)星解調(diào)器
文件頁(yè)數(shù)： 14/26頁(yè)
文件大小： 450K
代理商： ZL10313
ZL10313
Data Sheet
14
Zarlink Semiconductor Inc.
2.4.5 The Energy Dispersal (de-scrambler) Block, DVB Only
Before Reed-Solomon encoding in the DVB transmission system, the MPEG2 data stream is randomised using the
configuration shown in Figure 12 below. This is a Pseudo Random Binary Sequence (PRBS) generator, with the
polynomial:
1 + X
14
+ X
15
The PRBS registers are loaded with the initialisation sequence as shown, at the start of the first transport packet in
a group of eight packets. This point is indicated by the inverted sync byte 0xB8 (the normal DVB sync byte is 0x47).
The data starting with the first byte after the sync byte are randomised by exclusive-ORing data bits with the PRBS
(the sync bytes themselves are not randomised). In the decoder, the process of de-randomising or de-scrambling
the data is exactly the same as described above. The de-scrambler also inverts the sync byte 0xB8 so that all
MPEG output packets have the same sync byte 0x47.
Figure 12 - DVB Energy Dispersal Conceptual Diagram
2.4.6 Output Stage
The transport stream can be output in a byte-parallel or bit-serial mode. The output interface consists of an 8-bit
output, output clock, a packet validation level, a packet start pulse and a block error indicator.
The output clock rate depends on the symbol rate, QPSK/BPSK choice, convolutional (Viterbi) coding rate,
DVB/DSS choice and byte-parallel or bit-serial output mode. This rate is computed by ZL10313 to be very close to
the minimum required to output packet data without packet overlap. Furthermore, the packets at the output of
ZL10313 are as evenly spaced as possible to minimize packet position movement in the transport layer. The
maximum movement in the packet synchronization byte position is limited to ±1 output clock period.
2.5 Control
Automatic symbol rate search, code rate search, signal acquisition and signal tracking algorithms are built into the
ZL10313 using a sophisticated on-chip controller. The software interaction with the device is via a simple Command
Driven Control (CDC) interface. This CDC maps high level inputs such as symbol rates in MSps and frequencies in
MHz, to low level on-chip register settings. The on-chip control state machine and the CDC significantly reduces the
software overhead as well as the channel search times. There is also an option for the host processor to by-pass
both the CDC as well as the on-chip controller and take direct control of the QPSK demodulator. Once the ZL10313
has locked to the signal, any frequency offset can be read from the LNB_FREQ error registers 7 and 8. The
frequency synthesiser under the software control can be re-tuned in frequency to optimise the received signal
within the baseband filter bandwidth. Note that ZL10313 compensates for any frequency offsets before QPSK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
XOR
Initialisation sequence
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL10313QCG 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10313QCG1 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10313UBH 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Satellite Demodulator
ZL10320 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Digital Television PVR-on-a-Chip Processor
ZL10320/GAC 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Digital Television PVR-on-a-Chip Processor
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