參數(shù)資料
型號: ZL10210
廠商: Zarlink Semiconductor Inc.
英文描述: DVB-C Cable Channel Demodulator
中文描述: DVB - C的有線頻道解調(diào)器
文件頁數(shù): 11/21頁
文件大?。?/td> 570K
代理商: ZL10210
ZL10210
Data Sheet
11
Zarlink Semiconductor Inc.
2.2 MPEG
2.2.1 Data Output Header Format
Figure 6 - DVB Transport Packet Header Byte
Parameter
Symbol
Value
Unit
Min.
Max.
CLK clock frequency (Primary)
f
CLK
0
400
1
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
kHz
Bus free time between a STOP and START condition.
t
BUFF
200
ns
Hold time (repeated) START condition.
t
HD;STA
200
ns
LOW period of CLK clock.
t
LOW
1300
ns
HIGH period of CLK clock.
t
HIGH
600
ns
Set-up time for a repeated START condition.
t
SU;STA
200
ns
Data hold time (when input).
t
HD;DAT
100
ns
Data set-up time
t
SU;DAT
100
ns
Rise time of both CLK and DATA signals.
t
R
note
2
ns
Fall time of both CLK and DATA signals, (100pF to ground).
t
F
20
ns
Set-up time for a STOP condition.
t
SU;STO
200
ns
Table 3 - Timing of 2-Wire Bus
TEI
0
1
0
0
0
1
1
1
1st byte
2nd byte
Transport
Packet
Header
4 bytes
184 Transport packet bytes
188 byte packet output
MDO[7]
MDO[0]
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