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參數(shù)資料
| 型號： | ZL10037LCF1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 消費家電 |
| 英文描述： | Digital Satellite Tuner with RF Bypass |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC28 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220, QFN-28 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大小： | 410K |
| 代理商： | ZL10037LCF1 |
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ZL10037
Data Sheet
9
Zarlink Semiconductor Inc.
2.1 PLL Registers
There are four registers that control the PLL:
The PLF bit is the PLL lock detect circuit output. The PLF bit is set after 64 consecutive comparison cycles in lock.
A chip-wide reset initializes the lock detect output to 0.
The 2[
14:8
] bits are the MSB bits of the LO Divider divide value.
The 2[
7:0
] bits are the LSB bits of the LO Divider divide value. The division ratio of the LO divider is fully
programmable to integer values within the range of 240 to 32767.
Note
that when the LO Divider divide value is to be changed, the new value is not actually presented to the LO
Divider until all of the 15-bit control word 2[
14:0
] has been programmed. Register 0 and 1 must be therefore be
programmed (in any order) before the LO divider is updated even if the only data change is in one of the registers.
The C[1:0] bits set the programmed charge pump current
.
The charge pump current is automatically increased to the next setting dependent on the VCO sub band that has
been selected by the VCO tuning algorithm. This is to compensate for changes in VCO gain and so provide
consistent PLL performance across all sub bands. Programming the highest charge pump value will not allow the
value to be incremented, therefore this value should not be programmed.
The value read back for the charge pump current is the actual value in use for the selected sub band.
Bit Field
Name
Default
Type
Description
7
PLF
2
[14:8]
-
R
PLL Lock Flag
6:0
0
R/W
MSB bits of LO Divider register
Table 3 - Register 0
Bit Field
Name
2
[7:0]
Default
Type
Description
7:0
0
R/W
LSB bits of LO Divider register
Table 4 - Register 1
Bit Field
Name
Default
Type
Description
7:6
-
0
R/W
Test modes
5:4
C[1:0]
0
R/W
Charge pump current
3:0
R[3:0]
0
R/W
Reference divider ratio
Table 5 - Register 2
C[1]
C[0]
Typ
Units
0
0
400
uA
0
1
550
uA
1
0
750
uA
1
1
1000
uA
Table 6 - Charge Pump Currents
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PDF描述 |
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| ZL10037LCG1 | Digital Satellite Tuner with RF Bypass |
| ZL10038LDG | MULTIMETER, DIGITAL; Accuracy, AC voltage range:+/-1.5% rdg + 3 digits; Accuracy, DC current range:+/-2.5% rdg + 3 digits; Accuracy, DC voltage range:+/-1.2% rdg + 3 digits; Accuracy, resistance range:+/-1.5%rdg + 3 digits; Current RoHS Compliant: NA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL10037LCG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10037LCG1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10038LDG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
| ZL10039LCF | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Digital Satellite Tuner with RF Bypass |
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