參數(shù)資料
型號(hào): ZL10036LDF
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 消費(fèi)家電
英文描述: Digital Satellite Tuner with RF Bypass
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, QFN-40
文件頁數(shù): 21/38頁
文件大?。?/td> 939K
代理商: ZL10036LDF
ZL10036
Data Sheet
21
Zarlink Semiconductor Inc.
3.3.3 Internal Operation Indicators (X Bits)
These bits indicate internal logic states and are not required for normal use of the ZL10036.
3.4 Write Registers
The ZL10036 has twelve registers which can be programmed by addressing the device in its slave receiver mode,
setting the LSB of the address byte (the R/W bit) to a zero. After the master transmits the correct address byte, the
ZL10036 will acknowledge its address, and accept data in response to further clocks on the SCL line. At the end of
each byte, the ZL10036 will generate the acknowledge bit. The master can at this point, generate a stop condition,
or further clocks on the SCL line if further registers are to be programmed. If data is written after the twelfth register
(byte-13), it will be ignored.
3.4.1 Register Sub-Addressing
If some register bits require changing, but not all, it is not necessary to write to all the registers. The registers can be
addressed in pairs starting with the even numbered bytes, i.e., 2 & 3, 4 & 5, etc. Table 5 below shows the protocol
required to address any of the even numbered register bytes. It therefore follows that to write to register byte-7 for
instance, byte-6 must also be written first. Register pairs may be written in any order, as required by the software,
e.g., 10/11 may be followed by 4/5.
Data Bits
Byte Selected
7
(MSB)
6
5
4
0
X
X
X
2
1
0
X
X
4
1
1
0
0
6
1
1
0
1
8
1
1
1
0
10
1
1
1
1
12
‘X’
= Don’t care (content defines a register bit).
Table 5 - Byte Address Allocation in Write Mode
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