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參數(shù)資料
| 型號： | ZIF600 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 尋呼電路 |
| 英文描述： | Pager Synthesiser and 4FSK Demodulator |
| 中文描述： | TELECOM, PAGING DECODER, PDSO24 |
| 封裝： | QSOP-24 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 229K |
| 代理商： | ZIF600 |
5
ZIF600
Fig.5 Response of DATA0 and DATA1 to a
±
4.8kHz I/Q input
DIGITAL DEMODULATOR
By using digital signal processing techniques it is possible
to get a very robust demodulator for 4-level FSK. The
demodulator produces a digital level depending on the received
frequency. A digital data slicer is used to encode the DATA0
and DATA1 signals. Extra functions are included to give an
AFC signal to the 8 bit Trim DAC for the crystal oscillator. The
DAC output will lag the incoming data, and will require some
external filtering to smooth DAC transitions (it is recommended
to connect a 10
μ
F capacitor from DACOUT to Ground).
The demodulator receives "I" and "Q" signals from the
ZIF100. Fig.5 shows the DATA0 and DATA1 response to a 4
level I/Q input at
±
4.8kHz from te ZIF100. Table 5 maps the
input frequency represented by the I/Q demodulator inputs to
the DATA0 and DATA1 outputs.
The decoder will recover the symbol clock and sample the
DATA0 and DATA1 signals at the appropriate time. DATA1 will
have multiple edges during symbol transmissions.
In a typical application the ZIF600 receives real time control
from a decoder interface and provided the decoder with DATA0
and DATA1. Fig.6 illustrates the sequence of applied signals
from the Decoder in a typical application. Note that other
system ICs will require additional contol, and this may affect
the sequencing given.
DATA1
1
1
0
0
DATA0
0
1
1
0
Frequency Deviation
+4.8kHz
+1.6kHz
—1.6kHz
—4.8kHz
Table 5. Frequency map for DATA output pins
DSC2
0
1
0
1
DSC1
0
0
1
1
Demodulator Mode
Off, Hold Data Slicing and AFC loop values
On, Fast Tracking for Data Slicingand AFC loop
On, Slow Tracking for Data Slicingand AFC loop
Off, Hold applied to Data Slicing and AFC loop values
Table 6. Demodulator mode control
SRF
0
1
Symbol Rate
Symbol Rate Filter 1600sps
Symbol Rate Filter 3200sps
Table 7. Symbol rate filter control
I (4.8KHz)
Q
DATA0
DATA1
Symbol Transitions
Jitter
Typical Sampling Point
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