參數(shù)資料
型號: Z8S18033VSC
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: CONN HDR INVERSE 120POS 5ROW R/A
中文描述: 8-BIT, MICROPROCESSOR, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 50/70頁
文件大?。?/td> 387K
代理商: Z8S18033VSC
Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-50
P R E L I M I N A R Y
DS971800401
DMA SOURCE ADDRESS REGISTER CHANNEL 0
(SAR0: I/O Address = 20H to 22H) specifies the physical source address for channel 0 transfers. The register contains
20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 source can be mem-
ory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal.
DMA Source Address Register, Channel 0L
Mnemonic SAR0L
Address 20
DMA Source Address Register, Channel 0H
Mnemonic SAR0H
Address 21
DMA Source Address Register Channel 0B
Mnemonics SAR0B
Address 22
Figure 55. DMA Source Address Register 0L
Figure 56. DMA Source Address Register 0H
DMA Channel 0 Address
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
DMA Channel 0 Address
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
Figure 57. DMA Source Address Register 0B
DMA Channel B Address
--
--
--
--
--
--
--
7
6
5
4
3
2
1
--
0
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