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參數(shù)資料
| 型號： | Z8S18006FSC |
| 廠商： | ZiLOG, Inc. |
| 元件分類： | 微處理器 |
| 英文描述： | CAP 0.47UF 50V 10% X7R AXIAL TR-14 |
| 中文描述： | 強(qiáng)化Z180微處理器 |
| 文件頁數(shù)： | 18/70頁 |
| 文件大?。?/td> | 387K |
| 代理商： | Z8S18006FSC |
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Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
1-18
P R E L I M I N A R Y
DS971800401
If an interrupt source is individually disabled, it cannot
bring the Z80180/Z8S180/Z8L180 out of SLEEP mode. If
an interrupt source is individually enabled, and the IEF bit
is 1 so that interrupts are globally enabled (by an EI in-
struction), the highest priority active interrupt will occur,
with the return address being the instruction after the SLP
instruction. If an interrupt source is individually enabled,
but the IEF bit is 0 so that interrupts are globally disabled
(by a DI instruction), the Z80180/Z8S180/Z8L180 leaves
SLEEP mode by simply executing the following instruc-
tion(s).
This provides a technique for synchronization with high-
speed external events without incurring the latency im-
posed by an interrupt response sequence. Figure 14
shows the timing for exiting SLEEP mode due to an inter-
rupt request. Note that the Z80180/Z8S180/Z8L180 takes
about 1.5 clocks to restart.
IOSTOP Mode.
IOSTOP mode is entered by setting the
IOSTOP bit of the I/O Control Register (ICR) to 1. In this
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
IOSTOP mode is by resetting the IOSTOP bit in ICR to 0.
SYSTEM STOP Mode
. SYSTEM STOP mode is the com-
bination of SLEEP and IOSTOP modes. SYSTEM STOP
mode is entered by setting the IOSTOP bit in ICR to 1 fol-
lowed by execution of the SLP instruction. In this mode,
on-chip I/O and CPU stop operating, reducing power con-
sumption, but the PHI output continues to operate. Recov-
ery from SYSTEM STOP mode is the same as recovery
from SLEEP mode except that internal I/O sources (dis-
abled by IOSTOP) cannot generate a recovery interrupt.
IDLE
Z80180/Z8S180/Z8L180 into this mode by setting the
IOSTOP bit (ICR5) to 1, CCR6 to 0, CCR3 to 1 and exe-
cuting the SLP instruction. The oscillator keeps operating
but its output is blocked to all circuitry including the PHI
pin. DRAM refresh and all internal devices stop, but exter-
nal interrupts can occur. Bus granting to external masters
can occur if the BREST bit in the CPU control Register
(CCR5) was set to 1 before IDLE mode was entered.
Mode.
Software
can
put
the
The Z80180/Z8S180/Z8L180 leaves IDLE mode in re-
sponse to a Low on RESET, an external interrupt request
on NMI, or an external interrupt request on /INT0, /INT1 or
/INT2 that is enabled in the INT/TRAP Control Register. As
previously described for SLEEP mode, when the
Z80180/Z8S180/Z8L180 leaves IDLE mode due to an
NMI, or due to an enabled external interrupt request when
the IEF flag is 1 due to an EI instruction, it starts by per-
forming the interrupt with the return address being that of
the instruction after the SLP instruction.
If an external interrupt enables the INT/TRAP control reg-
ister while the IEF1 bit is 0, Z80180/Z8S180/Z8L180
leaves IDLE mode; specifically, the processor restarts by
executing the instructions following the SLP instruction.
Figure 14. SLEEP Timing
SLP 2nd Opcode
Fetch Cycle
SLEEP Mode
φ
T
2
T
3
T
1
T
2
T
S
T
S
T
1
/INTi, /NMI
A
0
-A
19
/HALT
M1
Opcode Fetch or Interrupt
Acknowledge Cycle
SLP 2nd Opcode Address
FFFFFH
T
2
T
3
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