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參數(shù)資料
| 型號： | Z86L71 |
| 廠商： | ZiLOG, Inc. |
| 英文描述： | IR/Low-Voltage Microcontroller |
| 中文描述： | 紅外/低電壓微控制器 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大小： | 349K |
| 代理商： | Z86L71 |
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Z86L70/71/75/C71
Zilog
IR/Low-Voltage Microcontroller
DS97LVO0500
P R E L I M I N A R Y
1-27
1
CTR2 (D)%02:
Counter/Timer16 Control Register.
CTR2 Description
T16_Enable.
This field enables T16 when set to 1.
Single/Modulo-N.
In Transmit Mode, when set to 0, the
counter reloads the initial value when terminal count is
reached. When set to 1, the counter stops when the termi-
nal count is reached.
In Demodulation Mode, when set to 0 , T16 captures and
reloads on detection of all the edges; when set to 1, T16
captures and detects on the first edge, but ignores the sub-
sequent edges. For details, see the description of T16 De-
modulation Mode.
Time_Out.
This bit is set when T16 times out (terminal
count reached). In order to reset it, a 1 should be written to
this location.
T16_Clock.
Defines the frequency of the input signal to
Counter/Timer16.
Capture_INT_Mask.
Set this bit to allow interrupt when
data is captured into LO16 and HI16.
Counter_INT_Mask.
Set this bit to allow interrupt when
T16 times out.
P35_Out.
This bit defines whether P35 is used as a normal
output pin or T16 output.
Field
Bit Position
Value
0*
1
0
1
Description
T16_Enable
7-------
R
W
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize Edge
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture Int.
Enable Data Capture Int.
Disable Time-Out Int.
Enable Time-Out Int.
P35 as Port Output
T16 Output on P35
Single/Modulo-N
-6------
R/W
0
1
0
1
0
1
0
1
Time_Out
--5-----
R
T16 _Clock
---43---
R/W
00
01
10
11
0
1
0
1
0
1
Capture_INT_Mask
-----2--
R/W
Counter_INT_Mask
------1-
R/W
P35_Out
-------0
R/W
Note:
* Indicates the value upon Power-On Reset
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