參數(shù)資料
型號(hào)： Z86E40
廠商： ZiLOG, Inc.
英文描述： Z8 4K OTP Microcontroller( Z8系列4k ROM一次可編程微控制器)
中文描述： Z8 4K的檢察官辦公室的微控制器（Z8系列4K的ROM的一次可編程微控制器）
文件頁數(shù)： 39/64頁
文件大?。?/td> 391K
代理商： Z86E40
Z86E30/E31/E40
Zilog
Z8 4K OTP Microcontroller
DS97Z8X0502
P R E L I M I N A R Y
39
1
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority Register (IPR). An interrupt
machine cycle is activated when an interrupt request is
granted. Thus, disabling all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. All interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit starting address of the interrupt service
routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests need service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling or both edge trig-
gered, and are programmable by the user. The software
may poll to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located
in bits D7 and D6 of the IRQ Register (R250). The
configuration is shown in Table 11.
Clock.
The on-chip oscillator has a high-gain, parallel-res-
onant amplifier for connection to a crystal, RC, ceramic
resonator, or any suitable external clock source (XTAL1 =
Input, XTAL2 = Output). The crystal should be AT cut, 10
KHz to 16 MHz max, with a series resistance (RS) less
than or equal to 100 Ohms.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor's recommended capacitor values
from each pin directly to device pin Ground. The RC oscil-
lator option can be selected in the programming mode.
The RC oscillator configuration must be an external resis-
tor connected from XTAL1 to XTAL2, with a frequency-set-
ting capacitor from XTAL1 to Ground (Figure 29).
Table 11. IRQ Register Configuration
IRQ
Interrupt Edge
D7
0
0
1
1
D6
0
1
0
1
P31
F
F
R
R/F
P32
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Figure 29. Oscillator Configuration
XTAL1
XTAL2
C1
C2
C1
C2
C1
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
Ceramic Resonator or
Crystal
C1, C2 = 47 pF TYP *
F = 8 MHz
LC
C1, C2 = 22 pF
L = 130
μ
H *
F = 3 MHz *
RC
@ 5V Vcc (TYP)
C1 = 100 pF
R = 2K
F = 6 MHz
External Clock
L
R
* Typical value including pin parasitics
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