參數(shù)資料
型號(hào)： Z86E3016PSC
廠(chǎng)商： ZILOG INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Z8 4K OTP Microcontroller
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁(yè)數(shù)： 46/66頁(yè)
文件大小： 453K
代理商： Z86E3016PSC
Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
46
P R E L I M I N A R Y
DS97Z8X0500
STOP-Mode Recovery Delay Selec
t (D5). The 5 ms RE-
SET delay after STOP-Mode Recovery is disabled by pro-
gramming this bit to a zero. A 1 in this bit will cause a 5 ms
RESET delay after STOP-Mode Recovery. The default
condition of this bit is 1. If the fast wake up mode is select-
ed, the STOP-Mode Recovery source needs to be kept ac-
tive for at least 5TpC.
STOP-Mode Recovery Level Select
(D6). A 1 in this bit
defines that a high level on any one of the recovery sourc-
es wakes the MCU from STOP mode. A 0 defines low level
recovery. The default value is 0.
Cold or Warm Start
(D7). This bit is set by the device
upon entering STOP mode. A "0" in this bit indicates that
the device has been reset by POR (cold). A "1" in this bit
indicates the device was awakened by a SMR source
(warm).
STOP-Mode Recovery Register 2 (SMR2)
. This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register. Bits D2, D3, and D4 must be 0.
Watch-Dog Timer Mode Register
(WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is disabled after Pow-
er-On Reset and initially enabled by executing the WDT in-
struction and refreshed on subsequent executions of the
WDT instruction. The WDT is driven either by an on-board
RC oscillator or an external oscillator from XTAL1 pin. The
POR clock source is selected with bit 4 of the WDT regis-
ter.
Note:
Execution of the WDT instruction affects the Z (Ze-
ro), S (Sign), and V (Overflow) flags.
WDT Time-Out Period
(D0 and D1). Bits 0 and 1 control
a tap circuit that determines the time-out periods that can
beobtained (Table 13). The default value of D0 and D1
are 1 and 0, respectively.
WDT During HALT Mode
(D2). This bit determines
whether or not the WDT is active during HALT mode. A "1"
indicates that the WDT is active during HALT. A "0" dis-
ables the WDT in HALT mode. The default value is 1.
WDT During STOP Mode
(D3). This bit determines
whether or not the WDT is active during STOP mode. A 1
indicates active during STOP. A "0" disables the WDT dur-
ing STOP mode. This is applicable only when the WDT
clock source is the internal RC oscillator.
Clock Source For WDT
(D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1, and the WDT is
stopped in STOP mode. The default configuration of this
bit is 0, which selects the RC oscillator.
Permanent WDT.
When this feature is enabled, the WDT
is enabled after reset and will operate in Run and Halt
mode. The control bits in the WDTMR do not affect the
WDT operation. If the clock source of the WDT is the inter-
nal RC oscillator, then the WDT will run in STOP mode. If
the clock source of the WDT is the XTAL1 pin, then the
WDT will not run in STOP mode.
Note: WDT time-out in Stop-Mode will not reset
SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data
Registers.
WDTMR Register Accessibility.
The WDTMR register is
accessible only during the
first 60
internal system clock
cycles from the execution of the first instruction after Pow-
er-On Reset, Watch-Dog reset or a STOP-Mode Recovery
Table 12. STOP-Mode Recovery Source
D4
0
0
0
D3
0
0
1
D2
0
1
0
SMR Source selection
POR recovery only
P30 transition
P31 transition (Not in analog
mode)
P32 transition (Not in analog
mode)
P33 transition (Not in analog
mode)
P27 transition
Logical NOR of Port 2 bits 0-3
Logical NOR of Port 2 bits 0-7
0
1
1
1
0
0
1
1
1
0
1
1
1
0
1
SMR:10
Operation
D1
0
0
1
D0
0
1
0
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
Table 13. Time-out Period of WDT
D1
0
0
1
1
D0
0
1
0
1
Time-out of
the Internal
RC OSC
5 ms
10 ms*
20 ms
80 ms
Time-out of
the System
Clock
128 SCLK
256 SCLK*
512 SCLK
2048 SCLK
Notes:
*The default setting is 10 ms.
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