參數(shù)資料
型號(hào): Z86E3016ESE
廠商: ZILOG INC
元件分類: 微控制器/微處理器
英文描述: Z8 4K OTP Microcontroller
中文描述: 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP28
封裝: WINDOWED, HERMETIC SEALED, CERDIP-28
文件頁(yè)數(shù): 44/66頁(yè)
文件大?。?/td> 453K
代理商: Z86E3016ESE
Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
44
P R E L I M I N A R Y
DS97Z8X0500
mode will reduce the drive of the oscillator (OSC). The de-
fault value is 1.
Note:
4 MHz is the maximum external
clock frequency when running in the low EMI oscillator
mode.
STOP-Mode Recovery Register
(SMR). This register se-
lects the clock divide value and determines the mode of
STOP-Mode Recovery (Figure 31). All bits are Write Only
except bit 7 which is a Read Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP Recovery and re-
set by a power-on cycle. Bit 6 controls whether a low or
high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4 of the
SMR register specify the STOP-Mode Recovery Source.
The SMR is located in Bank F of the Expanded Register
Group at address 0BH.
Figure 31. STOP-Mode Recovery Register
(Write-Only Except Bit D7, Which is Read-Only)
D7
D6
D5
D4
D3
D2
D1
D0
SMR (F) 0B
SCLK/TCLK Divide by 16
0 OFF
1 ON
Stop Mode Recovery Source
000 POR and/or External Reset
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0:3
111 P2 NOR 0:7
Stop Delay
0 OFF
1 ON
Stop Recovery Level
0 Low
1 High
Stop Flag
0 POR
1 Stop Recovery
*
Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
**
*
*
*
*
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
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