參數(shù)資料
型號(hào): Z84C90-12VSC
英文描述: I/O Port
中文描述: I / O端口
文件頁數(shù): 31/31頁
文件大?。?/td> 491K
代理商: Z84C90-12VSC
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This problem could happen under the following narrowly defined conditions:
7
CE signal is active throughout the Interrupt Acknowledge cycle.
7
The address on the bus, A3
A0, is
110b
.
7
During this time, bit D3 is 1.
7
At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal.
7
At the time period of CE active, IORQ active, and M1 returns to the inactive state; all
during the rising edge of the clock.
This problem is not the case with the Z80 CPU. However, other CPUs could be affected.
One of the possible workarounds is to add the condition
M1 not active
to generate a CE
signal.
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