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ELEPHONE
ORLDWIDE
: 408.558.8500 E
H
EADQUARTERS
MAIL
910 E. H
CSUPPORT
AMILTON
ZILOG
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Two independent, 0 to 10 mbps, full-duplex chan-
nels, each with two baud-rate generators (BRGS)
and one digital phase-locked loop (DPLL) for
clock recovery
32-Byte Data FIFO’s for each receiver and trans-
mitter
ASYNC mode with:
– 1–8 bits/character; 1/16 to two stop bits/charac-
ter in 1/16 bit increments
– Programmable clock factor
– Break detect and generation
– Odd, Even, Mark, Space, or no parity and fram-
ing error detection
Byte-oriented Synchronous mode with
– 1–8 bits/character
– 2- to 16-bit programmable SYNC character
– 16- or 32-Bit cyclic redundancy check (CRC)
and transmit-to-receive slaving (for X.21)
HDLC/SDLC mode with:
– 8-bit address compare
– Extended address field option
– 16- or 32-bit CRC
EATURES
– Programmable idle line condition
– Optional preamble transmission and loop mode
External character synchronous mode for receive
DMA interface with separate request and
acknowledge for each receiver and transmitter
G
ENERAL
D
ESCRIPTION
The Z16C30 USC Universal Serial Controller is a
dual-channel multi-protocol data communications
peripheral. Designed for use with any conventional
multiplexed or non-multiplexed bus, the USC
functions as a serial-to-parallel, parallel-to-serial
converter/controller, and may be software configured
to satisfy a wide variety of serial communications
applications. The device contains a variety of
sophisticated internal functions, including two baud
rate generators per channel, one digital phase-locked
loop per channel, character counters for both receive
and transmit in each channel, and 32-byte data
FIFO’s for each receiver and transmitter.
The CPU bus accesses have been shortened from 160
ns per access to 110 ns per access. The USC has a
transmit and receive clock range of up to 10 MHz (20
MHz when using the DPLL, BRG, or CTR to divide
the clock by 2 or more), and data transfer rates as
high as 10 Mbps (full duplex).
The
synchronous byte-oriented formats such as BISYNC,
and synchronous bit-oriented formats such as HDLC.
USC
handles
asynchronous
formats,
The device generates and checks CRC in any
synchronous mode and can be programmed to check
data integrity in various modes. The USC also has
facilities for modem controls in both channels. In
applications where these controls are not needed, the
modem controls may be used for general-purpose I/
O. The same holds true for most of the other pins in
each channel.
Interrupts are supported with a daisy-chain hierarchy,
with the two channels having completely separate
interrupt structures.
Modem/Control Logic
CTR
BRG
DPLL
BRG
CTR
CRC
Transmit
Logic
Receive
Logic
CRC
FIFO
FIFO
FIFO
Transmit
Logic
Receive
Logic
FIFO
CRC
CRC
CTR
BRG
DPLL
BRG
CTR
Modem/Control Logic
Z16C30
USC U
C
ONTROLLER
NIVERSAL
S
ERIAL
PB000300-SCC0399