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參數(shù)資料
| 型號： | YAC520-E |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 358K |
| 代理商： | YAC520-E |
YAC520
4
s Pin Functions
Power supply pins
Power supply pins
AVDD
––––
Analog power supply (+5.0 V)
AVSS
––––
Analog ground
DVDD
––––
Digital power supply (+5.0 V)
DVSS
––––
Digital ground
Analog Pins
Analog Pins
LIN1
––––
Left Channel Analog input 1
Lch analog input pin 1
Gain setting ranges from +32 dB to – 95 dB when the signal inputted to LIN2 is inputted this pin, and
gain setting ranges from +20.0 dB to – 107.0 dB when it is grounded through a capacitor.
LIN2
––––
Left Channel Analog input 2
Lch analog input pin 2
Gain setting ranges from +32 dB to – 95 dB when the signal inputted to LIN1 is inputted this pin, and
gain setting ranges from +29.5 dB to – 97.5 dB when it is grounded through a capacitor.
RIN1
––––
Right Channel Analog input 1
Rch analog input pin 1
Gain setting ranges from +32 dB to – 95 dB when the signal inputted to RIN2 is inputted this pin, and
gain setting ranges from +20.0 dB to – 107.0 dB when it is grounded through a capacitor.
RIN2
––––
Right Channel Analog input 2
Rch analog input pin 2
Gain setting ranges from +32 dB to – 95 dB when the signal inputted to RIN1 is inputted this pin, and
gain setting ranges from +29.5 dB to – 97.5 dB when it is grounded through a capacitor.
LOUT
––––
Left Channel Analog output
Lch analog output pin
Note this is an inverted output.
ROUT
––––
Right Channel Analog output
Rch analog output pin
Note this is an inverted output.
VREF
––––
Analog Reference Voltage (output)
Analog reference voltage output pin
Outputs 1/2VDD. Ground through a capacitor of 10
F or more to attain stabilization.
Digital Pins
Digital Pins
SDATAI
––––
Serial Data Input
Serial data input pin
SDATAO
––––
Serial Data Output
Serial data putput pin
Outputs Serial data when CSN is “l(fā)ow”, or becomes high impedance state when it is “high”.
SCLK
––––
Serial Clock (Input)
Serial clock input pin
CSN
––––
Chip Select (Input)
Chip select input pin
ICN
––––
DC Bias Initial Clear (Input)
DC bias initialization pin.
DC bias is set to VREF (analog reference voltage) when this is “l(fā)ow”.
To stabilize the bias voltage at power on, determine the control time in accordance with the coupling
capacitor that is connected to the inputs (LIN1, LIN2, RIN1 ,RIN2).
(Refer to “VREF stabilization time and DC bias initialization time” in the description of functions.)
ZCEN
––––
Zero Crossing Enable (Input)
Zero crossing control pin.
Making this pin “high” enables a mode where volume change is performed
after detecting zero crossing.
The volume change immediately after writing data when this pin is “l(fā)ow”.
TE
––––
Test Enable (Input)
Test mode control pin.
Fix it to “l(fā)ow” or with NC when using.
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