參數資料
型號: XRT95L51IB
廠商: EXAR CORP
元件分類: 數字傳輸電路
英文描述: STORAGE, SLIDES CABINET RoHS Compliant: Yes
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PBGA388
封裝: 35 X 35 MM, PLASTIC, BGA-388
文件頁數: 2/8頁
文件大?。?/td> 123K
代理商: XRT95L51IB
XRT95L51
OC-48 ATM UNI/POS/MAPPER IC
REV. P1.0.1
á
PRELIMINARY
2
FUNCTIONAL OVERVIEW
XRT95L51 implements the SONET/SDH framing
function with full duplex ATM/POS interface for the
STS-48/STM-16 data streams.The XRT95L51 is
functionally and architecturally, divided into the follow-
ing blocks and modules:
LINE SIDE INTERFACE
Differential inputs/outputs for high speed chip-to-
chip communication using Pseudo ECL logic.
Programmable parity bit for both incoming and out-
going data paths.
Monitors the Loss of Optical Carrier.
The transmit line side provides the direct looped
back version of the line clock, framing pulse and
parity.
The reference signal derived from the receive clock
input can be programmed to be 77.76 MHz,38.88
MHz,19.44 MHz or 8 kHz.
The reference signal derived from the transmit
clock input can be programmed to be 77.76
MHz,38.88 MHz, 19.44 MHz and 8 kHz.
8 kHz reference signal can be phase locked to
either incoming or outgoing SONET/SDH frame.
Supports Local and Remote Line Loopback.
Provides 155.52 MHz 16-bit parallel interface
SONET/SDH TRANSMITTER
Performs standard OC-48c/STM-16c transmit pro-
cessing
Conforms to IYU-T I.432,ANSI.105 and Bellcore
GR-253
Performs SONET/SDH frame insertion and accepts
external frame synchronization
Performs optional transmit data scrambling
Performs POH,TOH generation/insertion
Generates transmit payload pointer (H1,H2) (fixed
at 522) with NDF insertion
Inserts A1/A2 with optional error mask
Computes and inserts BIP-8 (B1,B2) with optional
error mask
Generates AIS-L,REI-L and RDI-L according to
receiver state with option of SW/HW insertion
Inserts LOS, forces SEF by software
Generates RDI-P and REI-P automatically with
optional SW/HW override
Inserts fixed stuff columns, calculates and inserts
B3 error code
Performs payload insertion from cell processor
SONET/SDH RECEIVER
Performs standard STS-48c/STM-16c receive pro-
cessing
Provides fully programmable threshold detection for
SD and SF condition
Provides 155.52MHz 16-bit parallel interface
Provides section trace buffer with mis-match detec-
tion and invalid message detection
Performs SONET/SDH frame synchronization
Supports NDF, positive stuff and negative stuff
pointer processor
Performs receive data de-scrambling
Performs POH,TOH interpretation/extraction
Interprets payload pointer (H1,H2)
Extracts data communication channels from D1-D3
and D4-D12
Detects out of frame (OOF), loss of frame (LOF),
loss of signal (LOS), APS failure
Detects Line Alarm Indication (L-AIS), Line remote
Defect Indication (L-RDI), Loss of Pointer
Detects Path Alarm Indication, Path remote Defect
Indication, Path extended RDI
Provides signal label monitor with PLM detection
Supports path travel buffer with TIM-P and invalid
message detection
Computes and compare B3,REI-L and REI-P errors
Computes and compare BIP-8 (B1,B2) and counts
the errors
Performs payload extraction.
ATM CELL PROCESSOR
Implements the ATM physical layer for Broadband
ISDN according to ITU-T Recommendation I.432
Supports SDH mapping
Provides selectable on-going HEC insertion and
verification
Provides selectable Coset addition and removal
Provides single bit error correction and multiple bit
error detection for HEC processing
Provides HEC correctable and uncorrectable indi-
cations
Provides HEC correction selectability
Supports external cell GFC insertion and extraction
Provides the functions of cell rate de-coupling; idle
cell insertion and detection, 16-cell FIFO cell buffer-
ing, programmable idle cell header and payload
and idle cell HEC generation
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