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參數(shù)資料
| 型號(hào)： | XRT95L34IV |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 123K |
| 代理商： | XRT95L34IV |
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XRT95L51
OC-48 ATM UNI/POS/MAPPER IC
PRELIMINARY
REV. P1.0.1
3
Offers cell delineation with three states (hunt, pre-
sync and sync) synchronization algorithm and pro-
vides LCD (Loss of Cell Delineation) indication and
interrupt
Supports multiple programmable VPI/VCI filters on
Transmit and Receive
Provides self-synchronizing SDH cell scrambling/
de-scrambling, x
43
+1
Supports OAM cell insertion and extraction with
dedicated cell store via microprocessor interface.
Transmission is enabled through semaphore
Provides TXCell and TXCell indication signals
Provides test cell generation and verification
PACKET OVER SONET (POS) PROCESSOR
Supports packet based link protocols by using byte
synchronous HDLC framing like PPPHDLC and
frame relay
32-bit extended Saturn POS-PHY host interface
clocked to 100 MHz
Performs transmit HDLC frame insertion and
receive data extraction
Performs self-synchronous data scrambling and de-
scrambling using1+X
43
polynomial
Performs transmit flag sequence insertion and
receive synchronization
Performs byte stuffing and de-stuffing for transpar-
ency processing
Performs optional CRC-CCITT and CRC-32 FCS
generation and error checking
Supports optionally flow-through mode
Performs abort sequence insertion and detection
Arbitrary packet length (1 or more octets) and flag
sharing (single flag between frames)
Provide minimum and maximum packet length
checking, removing and reporting
Transparency by octet stuffing of flag (0x7E), con-
trol escape (0x7D) and abort sequence
Automatic transfer halt on receive FIFO host-side at
end of packet
Error detection for Underflow of transmit FIFO,
Overflow of receive FIFO, parity error on transmit
Optional removal of FCS from receive frames
Optional transmit FCS insertion
UTOPIA / POS-PHY INTERFACE
Complies with ATM forum Utopia Level 2 and 3
Specification
Supports 32-bit 100MHz Transmit and Receive
interface
Provides up to total 16 cell buffers for transmit and
receive
Transmits and receives both 52 and 54 byte cell
Generates and checks data parity of Utopia inter-
face
Supports programmable Transmit CLAV (transmit
cell available) signal for 0,1,2,3 cell look ahead
Supports programmable Receive CLAV (receive
cell available) signal for 0,1,2,3 byte look ahead
Provides 32-bit up to 100 MHz industrial standard
POS-PHY interface
PERFORMANCE MONITORING
Supports line path performance monitoring
Provides 32-bit saturating counter of idle cells
transmitted
Provides 32-bit saturating counter of assigned cells
transmitted
Provides 32-bit saturating counter of valid cells
received
Provides 32-bit saturating counter of idle cells
received
Provides 32-bit saturating counter of cells received
with HEC error
Provides 32-bit saturating counter of cells dis-
carded
Provides 32-bit saturating counter of REI-L errors
Provides 32-bit saturating counter of REI-P errors
Provides 32-bit saturating counter of BIP-8 (B1,B2
and B3) errors
Provides 32-bit saturating counter of POS frame
check sequence errors
Provides 32-bit saturating PPP good frame counter
Provides 32-bit saturating PPP bad FCS counter
Provides 32-bit saturating PPP aborted frame
counter
Provides 32-bit saturating PPP Runt frame counter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT95L51 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OC-48 ATM UNI/POS/MAPPER IC |
| XRT95L51IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:OC-48 ATM UNI/POS/MAPPER IC |
| XRT95L53 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OC-48 ETHERNET/SONET MULTI-SERVICE FRAMER PROCESSOR |
| XRT95L53ES | 功能描述:界面開發(fā)工具 Eval System for XRT95L53 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR-TA | 功能描述:鉗型萬用表及配件 TEMPERATURE ADAPTER FOR 33XR 34XR 38XR RoHS:否 制造商:Fluke 準(zhǔn)確性:2 % 測(cè)距:400 A |
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