XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
REV. P1.0.3
II
F
IGURE
15. P
ARALLEL
R
EMOTE
L
OOPBACK
.................................................................................................................................... 23
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 24
F
IGURE
16. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 24
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 25
4.4.1 JITTER TOLERANCE:................................................................................................................................................ 25
F
IGURE
17. J
ITTER
T
OLERANCE
M
ASK
............................................................................................................................................ 25
4.4.2 JITTER TRANSFER.................................................................................................................................................... 26
4.4.3 JITTER GENERATION................................................................................................................................................ 26
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK .........................................................................27
F
IGURE
18. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 27
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 27
F
IGURE
19. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 27
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 28
5.2.1 R/W (SCLK1)............................................................................................................................................................... 28
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 28
5.2.3 X (DUMMY BIT SCLK8).............................................................................................................................................. 28
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 28
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 28
6.0 REGISTER MAP AND BIT DESCRIPTIONS .......................................................................................29
T
ABLE
7: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
.............................................................................................................. 29
T
ABLE
6: M
ICROPROCESSOR
R
EGISTER
M
AP
.................................................................................................................................. 29
T
ABLE
9: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
.............................................................................................................. 30
T
ABLE
8: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
.............................................................................................................. 30
T
ABLE
10: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 31
T
ABLE
11: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 33
T
ABLE
12: M
ICROPROCESSOR
R
EGISTER
B
IT
D
ESCRIPTION
............................................................................................................ 34
T
ABLE
13: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................. 35
T
ABLE
14: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................. 35
7.0 ELECTRICAL CHARACTERISTICS ...................................................................................................36
A
BSOLUTE
M
AXIMUMS
.................................................................................................................................36
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................36
196 S
HRINK
T
HIN
B
ALL
G
RID
A
RRAY
................................................................................................. 37
(12.0
MM
X
12.0
MM
, STBGA).......................................................................................................... 37
R
EV
. 1.00......................................................................................................................................... 37
ORDERING INFORMATION ..................................................................................................................37
R
EVISION
H
ISTORY
......................................................................................................................................38