參數(shù)資料
型號： XRT91L80IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 12 X 12 MM, STBGA-196
文件頁數(shù)： 5/45頁
文件大?。?/td> 359K
代理商： XRT91L80IB
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
II
F
IGURE
14. S
IMPLIFIED
D
IAGRAM
OF
THE
E
XTERNAL
L
OOP
F
ILTER
.................................................................................................. 23
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 23
F
IGURE
15. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE
BLOCK
.............................................................................................................. 23
4.0 DIAGNOSTIC FEATURES ...................................................................................................................24
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 24
F
IGURE
16. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 24
4.2 PARALLEL REMOTE LOOPBACK ............................................................................................................... 24
F
IGURE
17. P
ARALLEL
R
EMOTE
L
OOPBACK
.................................................................................................................................... 24
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 25
F
IGURE
18. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 25
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 26
4.4.1 JITTER TOLERANCE:................................................................................................................................................ 26
F
IGURE
19. J
ITTER
T
OLERANCE
M
ASK
............................................................................................................................................ 26
F
IGURE
20. 91L80 M
EASURED
JITTER
TOLERANCE
WITH
EXTERNAL
JITTER
ATTENUATION
ENABLED
IN
LOOPTIMING
AT
2.488 G
BPS
IN
STS-
48.................................................................................................................................................................................. 27
4.4.2 JITTER TRANSFER.................................................................................................................................................... 27
F
IGURE
21. 91L80 M
EASURED
JITTER
TRANSFER
WITH
EXTERNAL
JITTER
ATTENUATION
ENABLED
IN
LOOPTIMING
AT
2.488 G
BPS
IN
STS-
48.................................................................................................................................................................................. 27
4.4.3 JITTER GENERATION................................................................................................................................................ 28
F
IGURE
22. 91L80 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
T
RANSMIT
J
ITTER
G
ENERATION
AT
2.488 G
BPS
...................................... 28
F
IGURE
23. 91L80 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
R
ECEIVE
J
ITTER
G
ENERATION
AT
2.488 G
BPS
........................................ 28
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK .........................................................................29
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 29
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 29
F
IGURE
25. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 29
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 30
5.2.1 R/W (SCLK1)............................................................................................................................................................... 30
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 30
5.2.3 X (DUMMY BIT SCLK8).............................................................................................................................................. 30
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 30
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 30
6.0 REGISTER MAP AND BIT DESCRIPTIONS .......................................................................................31
T
ABLE
10: M
ICROPROCESSOR
R
EGISTER
M
AP
................................................................................................................................ 31
T
ABLE
11: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
................................................................................................. 31
T
ABLE
12: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................. 32
T
ABLE
13: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................. 32
T
ABLE
14: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
................................................................................................. 33
T
ABLE
15: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
................................................................................................. 35
T
ABLE
16: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
................................................................................................. 35
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
0
X
3E
H
B
IT
D
ESCRIPTION
................................................................................................. 37
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
0
X
3F
H
B
IT
D
ESCRIPTION
................................................................................................. 37
7.0 ELECTRICAL CHARACTERISTICS ...................................................................................................38
A
BSOLUTE
M
AXIMUM
RATINGS ..................................................................................................................38
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
....................................................................38
...................................................................................................................................................................39
C
OMMON
MODE
LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS ................................................39
...................................................................................................................................................................39
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS..........................................................39
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...............................................................40
LVTTL/LVCMOS S
IGNAL
DC ELECTRICAL CHARACTERISTICS ...........................................................40
ORDERING INFORMATION ..................................................................................................................41
R
EVISION
H
ISTORY
......................................................................................................................................42
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參數(shù)描述
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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