參數(shù)資料
型號： XRT91L32IQ
廠商： Exar Corporation
文件頁數(shù)： 18/37頁
文件大小： 0K
描述： IC TXRX SONET/SDH 8BIT 100QFP
產(chǎn)品變化通告： XRT91L32IQ(TR) Obsolescence 12/Oct/2010
標準包裝： 90
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
包裝： 托盤
xr
XRT91L32
REV. 1.0.3
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
23
3.3
Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or
155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface to an optical module. The
PISO bit interleaves parallel data input into a serial bit stream taking the first bit from TXDI7, then the first bit
from TXDI6, and so on as shown in Figure 13.
3.4
Clock Multiplier Unit (CMU) and Re-Timer
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK
reference clock is used, the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 1, on page 11 shows the CMU reference clock frequency settings. Table 12
specifies the Clock Multiplier Unit’s requirements for the reference clock.
TABLE 12: CLOCK MULTIPLIER UNIT REQUIREMETNS FOR REFERENCE CLOCK
FIGURE 13. SIMPLIFIED BLOCK DIAGRAM OF PISO
NAME
PARAMETER
MIN
TYP
MAX
UNITS
REFDUTY
Reference clock duty cycle
40
60
%
REFJIT
Reference clock jitter (rms) with 19.44 MHz reference1
5
ps
REFJIT
Reference clock jitter (rms) with 77.76 MHz reference1
13
ps
REFTOL
Reference clock frequency tolerance2
-20
+20
ppm
ECLKJIT
STS-3/STM-1 Electrical Clock output jitter (rms) with 19.44 MHz reference
1
mUIrms
ECLKJIT
STS-12/STM-4 Electrical Clock output jitter (rms) with 19.44 MHz reference
5
mUIrms
ECLKJIT
STS-3/STM-1 Electrical Clock output jitter (rms) with 77.76 MHz reference
2
mUIrms
b00
b01
b02
b03
b04
b05
b06
b07
bn0
bn1
bn2
bn3
bn4
bn5
bn6
bn7
bn+0
bn+1
bn+2
bn+3
bn+4
bn+5
bn+6
bn+7
b70
b71
b72
b73
b74
b75
b76
b77
8-bit Parallel LVTTL Input Data
TXDI0
TXDI7
TXDIn+
TXDIn
TXOP/N
TXPCLK_IO
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
622.08 Mbps STS-12/STM-4 or
155.52 Mbps STS-3/STM-1 serial data rate
b40
b50
b60
b70
b20
b30
b47
b57
b67
b77
b37
PI
S
O
time (0)
b27b17b07
b10 b00
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XRT91L32IQTR-F 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
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