參數(shù)資料
型號: XRT91L306
廠商: Exar Corporation
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: STS-12/STM-4或STS-3/STM-1的SONET / SDH收發(fā)器
文件頁數(shù): 12/39頁
文件大小: 440K
代理商: XRT91L306
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
xr
REV. 1.0.1
10
POWER AND GROUND
CAP1P
CAP2P
Analog
-
39
42
CDR Non-polarized External Filter Capacitor
C1 = 0.47
μ
F ± 10% tolerance
(Isolate from noise and place close to pin)
CAP1N
CAP2N
Analog
-
40
41
CDR Non-polarized External Filter Capacitor
C2 = 0.47
μ
F ± 10% tolerance
(Isolate from noise and place close to pin)
DLOSDIS
LVTTL,
LVCMOS
I
7
LOS (Los of Signal) Detect Disable
Disables internal LOS monitoring and automatic muting of
RXDO[7:0] upon LOS detection (according to gating shown in
figure 7). LOS is declared when
a string of 128 consecutive
zeros occur on the line. LOS condition is cleared when the 16
or more pulse transitions is detected for 128 bit period sliding
window.
"Low" = Monitor and Mute received data upon LOS declaration
"High" = Disable LOS monitoring (see Figure 7 for logical oper-
ation).
LOSEXT
SE-LVPECL
I
33
LOS or Signal Detect Input from Optical Module
Active "Low." When active, this pin can force the received data
output bus RXDO[7:0] to a logic state of ’0’ per Figure 7.
"Low" = Forced LOS
"High" = Normal Operation
N
AME
T
YPE
P
IN
D
ESCRIPTION
VDD3.3
PWR
15, 18, 31, 34, 47, 61
3.3V CMOS Power Supply
VDD3.3 should be isolated from the Analog VDD power supplies.
Use a ferrite bead along with an internal power plane separation.
The VDD3.3 power supply pins should have bypass capacitors to
the nearest ground. For best results, refer to Application notes
about board layout guidelines.
AVDD3.3_TX
PWR
38
Analog 3.3V Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
AVDD3.3_RX
PWR
43
Analog 3.3V Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
VDD_PECL
PWR
4, 10
3.3V Input/Output LVPECL Bus Power Supply
These pins require a 3.3V potential voltage for properly biasing
the Differential LVPECL input and output pins.
AGND_TX
PWR
37
Transmitter Analog Ground for 3.3V Analog Power Supplies
It is recommended that all ground pins of this device be tied
together.
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
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