TABLE
參數(shù)資料
型號: XRT86VL38IB
廠商: Exar Corporation
文件頁數(shù): 113/160頁
文件大小: 0K
描述: IC LIU/FRAMER T1/E1/J1 8CH 420BG
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 420-BBGA
供應(yīng)商設(shè)備封裝: 420-PBGA
包裝: 托盤
XRT86VL38
51
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 34: RECEIVE INTERFACE CONTROL REGISTER (RICR)
HEX ADDRESS: 0XN122
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RxSyncFrD
R/W
0
Receive Synchronous fraction data interface
This bit selects whether RxCHCLK or RxSERCLK will be used for fractional
data output if receive fractional interface is enabled. If RxSERCLK is selected
to clock out fractional data, RxCHCLK will be used as an enable signal
0 = Fractional data Is clocked out of the chip using RxChCLK if the receive
fractional interface is enabled.
1 = Fractional data is clocked out of the chip using RxSerClk if the receive
fractional interface is enabled. RxChClk is used as fractional data enable.
NOTE: The Time Slot Identifier Pins (RxChn[4:0]) still indicates the time slot
number if the receive fractional data interface is not enabled.
Fractional Interface can be enabled by setting RxFr1544 to 1
6
Reserved
-
Reserved
5
RxPLClkEnb/
RxSync is low
R/W
0
Receive payload clock enable/RxSYNC is Active Low
This exact function of this bit depends on whether the T1 framer is configured
to operate in base rate or high speed modes of operation.
If the T1 framer is configured to operate in base rate - TxPayload Clock:
This bit configures the T1 framer to either output a regular clock or a payload
clock on the receive serial clock (RxSERCLK) pin when RxSERCLK is config-
ured to be an output.
0 = Configures the framer to output a 1.544MHz clock on the RxSERCLK pin
when RxSERCLK is configured as an output.
1 = Configures the framer to output a 1.544MHz clock on the RxSERCLK pin
when receiving payload bits. There will be gaps on the RxSERCLK output pin
when receiving overhead bits.
If the T1 framer is configured to operate in high-speed or multiplexed
modes - RxSYNC is Active Low:
This bit is used to select whether the receive frame boundary (RxSYNC) is
active low or active high.
0 = Selects RxSync to be active “High”
1 = Selects RxSync to be active “Low”
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