參數資料
型號: XRT86VL38_2
廠商: Exar Corporation
元件分類: 通信及網絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數: 96/160頁
文件大?。?/td> 860K
代理商: XRT86VL38_2
XRT86VL38
91
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
80: B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(BISR) H
EX
A
DDRESS
: 0
X
nB00
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Reserved
For E1 mode only
6
LBCODE
RO
0
Loopback Code Block Interrupt Status
This bit indicates whether or not the Loopback Code block has an
interrupt request awaiting service.
0 - Indicates no outstanding Loopback Code Block interrupt request
is awaiting service
1 - Indicates the Loopback Code block has an interrupt request
awaiting service. Interrupt Service routine should branch to the inter-
rupt source and read the Loopback Code Interrupt Status register
(address 0xnB0A) to clear the interrupt
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the Loopback Code Interrupt Status
Register.
5
RxClkLOS
RO
0
Loss of Recovered Clock Interrupt Status
This bit indicates whether or not the framer has experienced a Loss
of Recovered Clock interrupt since last read of this register.
0 = Indicates Loss of Recovered Clock interrupt has not occurred
since last read of this register
1 = Indicates Loss of Recovered Clock interrupt has occurred since
last read of this register.
N
OTE
:
This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4
ONESEC
RO
0
One Second Interrupt Status
This bit indicates whether or not the framer has experienced a One
Second interrupt since the last read of this register.
0 = Indicates One Second interrupt has not occurred since the last
read of this register
1 = Indicates One Second interrupt has occurred since the last read
of this register
3
HDLC
RO
0
HDLC Block Interrupt Status
This bit indicates whether or not the HDLC block has any interrupt
request awaiting service.
0 = Indicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicates HDLC Block has an interrupt request awaiting service.
Interrupt Service routine should branch to the interrupt source and
read the corresponding Data LInk Status Registers (address
0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the
interrupt.
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generated the interrupt.
相關PDF資料
PDF描述
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關代理商/技術參數
參數描述
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