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參數(shù)資料
| 型號： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 1/43頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XRT82L24IV |
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Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
á
XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MARCH 2003
REV. 1.2.3
GENERAL DESCRIPTION
The XRT82L24 is a fully integrated Quad (four chan-
nels) short-haul line interface unit for E1(2.048Mbps)
75
or 120
applications. Each channel consists of a
receiver with equalizer for reliable data and clock re-
covery, and a transmitter which accepts either single
or dual-rail digital inputs for signal transmission to the
line using a low output impedance line driver. The de-
vice also includes a crystal-less jitter attenuator
which, depending on system requirements, can be
selected in the receive or transmit path through the
Host or Hardware Mode control.
XRT82L24 is a low power CMOS device operating on
a single 3.3V supply with 5V tolerant digital inputs.
FEATURES
Fully integrated quad, short-haul PCM transceivers
for E1 applications.
On Chip Receive Equalizer and Transmit Pulse
Shaper for CEPT 75
and 120
line terminations
On chip clock recovery circuit
Transformer or capacitor coupled receiver inputs
Crystal-less jitter attenuator can be selected in the
transmit or receive path
High receiver interference immunity
Per-channel transmit power shutdown
Tri-state transmit output capability
On chip per-channel driver failure monitoring circuit
On chip HDB3/B8ZS/AMI encoder/decoder func-
tions
Transmit return loss meets or exceeds ETSI 300
166 standard
Meets or exceeds specifications in ITU G.703,
G.775, G.736 and G.823; ETSI 300-166
3.3V or 5.0V Logic level inputs
Single +3.3V Supply Operation
Same pin Out as XRT82L34 T1/E1/J1 LIU
New Patent# 6,313,671B1 Low Power IC I/O Buffer
APPLICATIONS
Digital cross connects (DSX-1)
Channel Banks
High speed data transmission line cards
E1 Multiplexer
Public switching systems and PBX interfaces
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT82L24 E1 LIU (H
OST
M
ODE
)
HDB3
Encoder
MUX
Tx/Rx Jitter
Attenuator
Tx Timing
Control
Tx Pulse
Shaper
MUX
Line
Driver
Tx/Rx Jitter
Attenuator
Timing & Data
Recovery
Peak
Detector
& Slicer
Rx
Equalizer
LOS
Detect
HDB3
Decoder
Clock
Generator
MClk
TVDD_n
TTIP_n
TRing_n
TGND_n
Enable/
Disable
RTIP_n
RRing_n
Remote
LoopBack
Local
Analog
LoopBack
Digital
LoopBack
Driver
Monitor
Channel 0
Channel 1
Channel 2
Channel 3
HW/HOST
μ
P Controller & Hardware Interface
ADD [0:3]
D[0:7]
WR_R/W/TxOFF_0
ALE_AS/TxOFF_2
CS/TxOFF_3
RD_DS/TxOFF_1
Test
TxClk_n/RZData_n
TxPOS_n/TDATA_n
TxNEG_n
RxClk_n
RxPOS_n/RDATA_n
RxNEG_n/LCV_n
RxLOS_n
INT
RDY_DTACK
PClk/Codes
PTS1/ClkE
PTS2/SR_DR
Reset
ICT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT82L24 | Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復(fù)和振動衰減器）) |
| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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