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參數(shù)資料
| 型號(hào)： | XRT8001 |
| 廠商： | Exar Corporation |
| 英文描述： | WAN Clock for T1 and E1 Systems |
| 中文描述： | 廣域網(wǎng)時(shí)鐘T1和E1系統(tǒng) |
| 文件頁數(shù)： | 19/48頁 |
| 文件大小： | 1054K |
| 代理商： | XRT8001 |
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XRT8001
19
Rev. 1.01
In the “High Speed – Reverse” Mode
In the “High Speed – Reverse” Mode, the XRT8001
WAN Clock will be receiving a 64kHz clock signal via
the “FIN” input pin. The XRT8001 WAN Clock will, in
response, generate an “M x 2.048MHz” clock via the
CLK1 and CLK2 output pins. These five (5) bit-fields
within Command Register CR2 are used to define the
value “M” for the CLK1 output.
Note:
The only acceptable values for “M” are 1, 2, 4, or 8.
3.2.4 Command Register CR3 (Address = 0x03)
D4 – D0 (SEL2[4:0])
These bit-fields are used to support configuration
implementation for the “Forward/Master” and the “High
Speed – Reverse” Modes of operation.
In the “Forward/Master” Mode
In the “Forward/Master” Mode, the XRT8001 WAN
Clock will output either a “K x 56kHz” or a “K x 64kHz”
clock signal via the CLK2 output pin. These five (5) bit-
fields within Command Register CR3 are used to define
the value of “K” for the CLK2 Output. As a conse-
quence, the XRT8001 can be configured to generate a
maximum frequency of “32 x 56kHz” or “32 x 64kHz” via
the CLK2 output pin.
In the “High Speed – Reverse” Mode
In the “High Speed – Reverse” Mode, the XRT8001
WAN Clock will be receiving a 64kHz clock signal via
the “FIN” input pin. The XRT8001 WAN Clock will, in
response, generate an “M x 2.048MHz” clock via the
CLK1 and CLK2 output pins. These five (5) bit-fields
within Command Register CR3 are used to define the
value “M” for the CLK2 output.
Note:
The only acceptable values for “M” are 1, 2, 4, or 8.
3.2.5 Command Register CR4 (Address = 0x04)
D4 – SYNCEN (SYNC Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the SYNC output
pin. Setting this bit-field to “1” enables this Driver.
Setting this bit-field to “0” disables this Driver.
D3 – CLK1EN (CLK1 Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the CLK1 output pin.
Setting this bit-field to “1” enables this Driver. Setting
this bit-field to “0” disables this Driver.
D2 – CLK2EN (CLK2 Output Driver Enable Select)
This “read/write” bit-field permits the user to enable or
disable the Driver associated with the CLK2 output pin.
Setting this bit-field to “1” enables this Driver. Setting
this bit-field to “0” disables this Driver.
D1, D0 – LDETDIS[2:1] – Lock Detector Output Control
The combination of these two bit-fields permit the user
to specify the signal that will be output via the
LOCKDET output pin. The user’s options are shown in
Table 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT8001ID | WAN Clock for T1 and E1 Systems |
| XRT8001IP | WAN Clock for T1 and E1 Systems |
| XRT8010 | 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
| XRT8010IL | 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
| XRT8020 | 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT8001ES | 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001ID | 制造商:Exar Corporation 功能描述:WAN Clock 18-Pin SOIC W |
| XRT8001ID-F | 功能描述:鎖相環(huán) - PLL 3.3V-5V temp -45 to 85C RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8001ID-F | 制造商:Exar Corporation 功能描述:WAN Clock IC |
| XRT8001IDTR-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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