TABLE
參數(shù)資料
型號(hào): XRT75R12IB-L
廠商: Exar Corporation
文件頁數(shù): 69/90頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝: 40
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 12/12
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 420-TBGA(35x35)
包裝: 托盤
XRT75R12
68
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 32: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 4
Reserved
3
Change of FL Con-
dition Interrupt Sta-
tus
RUR
Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change of FL
Condition Interrupt (for Channel n) has occurred since the last read of this
register.
0 - Indicates that the Change of FL Condition Interrupt has NOT occurred
since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has occurred since
the last read of this register.
NOTE: The user can determine the current state of the FIFO Alarm condition
by reading out the contents of Bit 3 (FL Alarm Declared) within the
Alarm Status Register.(n)
2
Change of LOL Con-
dition Interrupt Sta-
tus
RUR
Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch
n:
This RESET-upon-READ bit-field indicates whether or not the Change of
Receive LOL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOL Defect
condition by reading out the contents of Bit 2 (Receive LOL Defect
Declared) within the Alarm Status Register.(n)
1
Change of LOS
Condition Interrupt
Status
RUR
Change of Receive LOS (Loss of Signal) Defect Condition Interrupt
Status: Ch_n
This RESET-upon-READ bit-field indicates whether or not the Change of the
Receive LOS Defect Condition Interrupt (for Channel n) has occurred since
the last read of this register.
0 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has NOT occurred since the last read of this register.
1 - Indicates that the Change of the Receive LOS Defect Condition Interrupt
has occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOS Defect
condition by reading out the contents of Bit 1 (Receive LOS Defect
Declared) within the Alarm Status Register.(n)
0
Change of DMO
Condition Interrupt
Status
RUR
Change of Transmit DMO (Drive Monitor Output) Condition Interrupt
Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change of the
Transmit DMO Condition Interrupt (for Channel n) has occurred since the
last read of this register.
0 - Indicates that the Change of the Transmit DMO Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of the Transmit DMO Condition Interrupt has
occurred since the last read of this register.
NOTE:
The user can determine the current state of the Transmit DMO
Condition by reading out the contents of Bit 0 (Transmit DMO
Condition) within the Alarm Status Register.(n)
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