參數(shù)資料
型號(hào)： XRT75L06IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 52/63頁(yè)
文件大小： 0K
描述： IC LIU E3/DS3/STS-1 6CH 217BGA
標(biāo)準(zhǔn)包裝： 60
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 6/6
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 217-BBGA
供應(yīng)商設(shè)備封裝： 217-BGA（23x23）
包裝： 托盤(pán)
XRT75L06
REV. 1.0.3
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
53
0x04 (ch 0)
0x14 (ch 1)
0x24 (ch 2)
0x34 (ch 3)
0x44 (ch 4)
0x54 (ch 5)
R/W
Transmit
Control
D0
TxLEV_n
This bit should be set when the transmitter is driving
a line greater than 225 feet in the DS3 or STS-1
modes. It is not active in E3 mode.
0
D1
TxCLKINV
_n
Set this bit to sample the data on TPOS/TNEG pins
on the rising edge of TxCLK.Default is to sample on
the falling edge of TxCLK.
0
D2
TAOS_n
This bit should be set to transmit a continuous “all
ones” data pattern. Timing will come from TxCLK if
available otherwise from channel refernce clock.
0
D3
Reserved
D4
INSPRBS_
n
This bit causes a single bit error to be inserted in the
transmitted PRBS pattern if the PRBS generator/
detector has been enabled.
0
D5
TxMON_n
When set, this bit enables the DMO circuit to moni-
tor its own channel’s transmit driver. Otherwise, it
uses the MTIP/MRING pins to monitor another
channel or device.
0
D7-D6
Reserved
0x05 (ch 0)
0x15 (ch 1)
0x25 (ch 2)
0x35 (ch 3)
0x45 (ch 4)
0x55 (ch 5)
R/W
Receive
Control
D0
REQEN_n
This bit enables the Receiver Equalizer. When set,
the equalizer boosts the high frequency components
of the signal to make up for cable losses.
NOTE: See section 5.01 for detailed description.
0
D1
RxMON_n
Set this bit to place the Receiver in the monitoring
mode. In this mode, it can process signals (at RTIP/
RRING) with 20dB of flat loss. This mode allows the
channel to act as monitor of aline without loading the
circuit.
0
D2
LOSMUT_
n
When set, the data on RPOS/RNEG is forced to
zero when LOS occurs. Thus any residual noise on
the line is not output as spurious data.
NOTE: If this bit has been set, it will remain set evan
after the LOS condition is cleared.
0
D3
RxCLKINV
_n
When this bit is set, RPOS and RNEG will change
on the falling edge of RCLK.Default is for the data to
change on the rising edge of RCLK and be sampled
by the terminal equipment on the falling edge of
RCLK.
0
D4
ALOSDIS_
n
This bit is set to disable the ALOS detector. This flag
and the DLOSDIS are normally used in diagnostic
mode. Normal operation of DS3 and STS-1 would
have ALOS disabled.
0
D5
DLOSDIS_
n
This bit disables the digital LOS detector. This would
normally be disabled in E3 mode as E3 is a function
of the level of the input.
0
D7-D6
Reserved
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
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