參數(shù)資料
型號(hào): XRT75L04IV
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
中文描述: DATACOM, PCM TRANSCEIVER, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, LQFP-176
文件頁(yè)數(shù): 1/57頁(yè)
文件大?。?/td> 345K
代理商: XRT75L04IV
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
JULY 2006
REV. 1.0.4
GENERAL DESCRIPTION
The XRT75L04 is a four-channel fully integrated Line
Interface Unit (LIU) with Jitter Attenuator for E3/DS3/
STS-1 applications. It incorporates four independent
Receivers, Transmitters and Jitter Attenuators in a
single 176 pin LQFP package.
Each channel of the XRT75L04 can be configured to
operate in E3 (34.368 MHz), DS3 (44.736 MHz) or
STS-1 (51.84 MHz) rates that are independent of
each other. Each transmitter can be turned off and tri-
stated for redundancy support and for conserving
power.
The XRT75L04’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
The XRT75L04 incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter
attenuator performance meets the ETSI TBR-24 and
Telcordia GR-499, GR-253 specifications.
The XRT75L04 provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L04 supports local, remote and digital
loop-backs. The XRT75L04 also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
RECEIVER:
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
Detects and Clears LOS as per G.775.
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
On-chip
clock
synthesizer
appropriate rate clock from a single frequency
XTAL.
generates
the
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
TRANSMITTER:
Compliant with Telcordia GR-499, GR-253 and
ANSI T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitters can be turned on or off.
JITTER ATTENUATOR:
On chip advanced crystal-less Jitter Attenuator.
Jitter Attenuators can be selected in Receive or
Transmit paths.
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499-
CORE,1995 standards.
Meets ETSI TBR 24 Jitter Transfer Requirements.
16 or 32 bits selectable FIFO size.
Meets the Wander specifications described in
T1.105.03b.
Jitter Attenuators can be disabled.
CONTROL AND DIAGNOSTICS:
Serial Microprocessor Interface for control and
configuration.
Supports
optional
internal
Monitoring.
PRBS error counter register to accumulate errors.
Supports Local, Remote and Digital Loop-backs.
Single 3.3 V ± 5% power supply.
5 V Tolerant I/O.
Maximum Power Dissipation 1.5W.
Available in 176 pin LQFP package
- 40°C to 85°C Industrial Temperature Range.
Transmit
Driver
APPLICATIONS
E3/DS3 Access Equipment.
STS1-SPE to DS3 Mapper.
DSLAMs.
Digital Cross Connect Systems.
CSU/DSU Equipment.
Routers.
相關(guān)PDF資料
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