
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
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PRELIMINARY
XRT75L03D
THREE-CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
APRIL 2002
REV. P1.0.0
GENERAL DESCRIPTION
The XRT75L03D is a Three-Channel fully integrated
Line Interface Unit (LIU) and Jitter Attenuator for E3/
DS3/STS-1 applications. It incorporates three
independent Receivers, Transmitters and Jitter
Attenuators in a single 128-Lead QFP package.
Each channel of the XRT75L03D can be
independently configured to operate in E3 (34.368
MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz)
rates. Each transmitter can be turned off and tri-
stated for redundancy support and power
conservation.
The XRT75L03D’s differential receivers provide high
noise interference margin and are able to receive the
data over 1000 feet of cable, or with cable attenuation
of up to 12 dB.
The XRT75L03D incorporates an advanced crystal-
less jitter attenuator per channel that can be selected
either in the transmit or receive path. The jitter attenu-
ator performance meets the ETSI TBR-24 and
Bellcore GR-499 specifications. Also the jitter attenu-
ator can be used for clock smoothing in SONET STS-
1 to DS3 de-mapping.
The XRT75L03D provides both Serial Microprocessor
Interface as well as Hardware mode for programming
and control.
The XRT75L03D supports local,remote and digital
loop-backs. The XRT75L03D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
FEATURES
Receiver:
On chip Clock and Data Recovery circuit for high
input jitter tolerance
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Detects and Clears LOS as per G.775
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
On-chip Clock Synthesizer generates the appropri-
ate rate clock from a single frequency Crystal
Provides low jitter clock outputs for either E3, DS3
or STS-1 rates
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
Transmitter:
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
Tri-state Transmit output capability for redundancy
applications
Transmitter can be turned on or off
Jitter Attenuator:
On chip advanced crystal-less Jitter Attenuators
Jitter Attenuators can be selected in Receive or
Transmit paths
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-253 and GR-499-
CORE,1995 standards
Meets ETSI TBR 24 Jitter Transfer Requirements
16, 32 or 128 bits selectable FIFO size
De-Synchronizer for SONET STS-1 to DS3 de-
mapping
Meets the Jitter and Wander specifications
described in the ANSI T1.105.03b
Jitter Attenuators can be disabled
Control and Diagnostics:
5 wire Serial Microprocessor Interface for control
and configuration
Supports optional internal Transmit Driver Monitor-
ing
PRBS Error Counter Register to accumulate errors
Hardware Mode for control and configuration
Supports Local, Remote and Digital Loop-backs
Single 3.3 V ± 5% power supply
5 V Tolerant I/O
Available in 128 pin TQFP
-40°C to 85°C Industrial Temperature Range
APPLICATIONS
E3/DS3 Access Equipment
STS1-SPE to DS3 Mapper
DSLAMs
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals