TABLE 18: R
參數(shù)資料
型號: XRT73R06IB-F
廠商: Exar Corporation
文件頁數(shù): 54/68頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 6CH 217BGA
標(biāo)準(zhǔn)包裝: 126
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 6/6
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 217-BBGA
供應(yīng)商設(shè)備封裝: 217-BGA(23x23)
包裝: 托盤
XRT73R06
á
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
55
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
0x01 (ch 0)
0x11 (ch 1)
0x21 (ch 2)
0x31 (ch 3)
0x41 (ch 4)
0x51 (ch 5)
R/W
Interrupt
Enable
(source
level)
D0
DMOIE_n
If the Driver Monitor (connected to the output of the
channel) detects the absence of pulses for 128 con-
secutive cycles, it will set the interrupt flag if this bit
has been set.
0
D1
RLOSIE_n This flag will allow a loss of receive signal(for that
channel) to send an interrupt to the Host when this
bit is set.
0
D2
RLOLIE_n
This flag will allow a loss of lock condition to send an
interrupt to the Host when this bit is set.
0
D3
Reserved
This bit is Reserved.
0
D4
PRBSERIE
_n
Set this bit to enable the interrupt when the PRBS
error is detected.
0
D5
PRBSERC
NTIE_n
Set this bit to enable the interrupt when the PRBS
error count register saturates.
0
D6-D7
Reserved
0x02 (ch 0)
0x12 (ch 1)
0x22 (ch 2)
0x32 (ch 3)
0x42 (ch 4)
0x52 (ch 5)
Reset
on
Read
Interrupt
Status
(source
level)
D0
DMOIS_n
If the Drive monitor circuot detects the absence of
pulses for 128 consecutive cycles, t will set this
interrupt status flag (if enabled) This bit is set on a
change of state of the DMO circuit.
0
D1
RLOSIS_n This flag will indicate a change of “l(fā)oss of Receive
signal” to the Host when this bit is set.
0
D2
RLOLIS_n
This flag will allow a change in the loss of lock condi-
tion to send an interrupt to the Host when this bit is
enabled.Loss of lock is defined as a difference of
greater than 0.5% between the recovered clock and
the channel’s reference clock. Any change (return to
lock) will trigger the interrupt status flag again.
0
D3
Reserved
This bit is Reserved.
0
D4
PRBSERIS
_n
This bit is set when the PRBS error occurs.
0
D5
PRBSERC
NTIS_n
This bit is set when the PRBS error count register
saturates.
0
D7-D6
Reserved
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