參數(shù)資料
型號(hào)： XRT73L06
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： 六通道線路接口單元E3/DS3/STS-1
文件頁數(shù)： 5/63頁
文件大?。?/td> 348K
代理商： XRT73L06
XRT73L06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
II
3.3.1 B3ZS Encoding .................................................................................................................................. 26
3.3.2 HDB3 Encoding .................................................................................................................................. 26
Figure 17. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 26
Figure 18. B3ZS Encoding Format ................................................................................................................. 26
3.4 T
RANSMIT
P
ULSE
S
HAPER
............................................................................................................................... 27
Figure 20. Transmit Pulse Shape Test Circuit ................................................................................................ 27
3.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 27
Figure 19. HDB3 Encoding Format ................................................................................................................ 27
3.5 E3
LINE
SIDE
PARAMETERS
.............................................................................................................................. 28
Figure 21. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... 28
T
ABLE
3: E3 T
RANSMITTER
LINE
SIDE
OUTPUT
AND
RECEIVER
LINE
SIDE
INPUT
SPECIFICATIONS
.......................... 29
Figure 22. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ......... 30
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................ 30
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) . 31
Figure 23. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ 31
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT
AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) .... 32
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................... 32
3.6 T
RANSMIT
D
RIVE
M
ONITOR
.............................................................................................................................. 33
3.7 T
RANSMITTER
S
ECTION
O
N
/O
FF
....................................................................................................................... 33
Figure 24. Transmit Driver Monitor set-up. ..................................................................................................... 33
4.0 Jitter .................................................................................................................................................. 34
4.1 J
ITTER
T
OLERANCE
.......................................................................................................................................... 34
4.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 34
Figure 25. Jitter Tolerance Measurements ..................................................................................................... 34
4.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 35
Figure 26. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 35
Figure 27. Input Jitter Tolerance for E3 ......................................................................................................... 35
4.2 J
ITTER
T
RANSFER
............................................................................................................................................ 36
T
ABLE
8: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ....................................... 36
T
ABLE
9: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................. 36
T
ABLE
10: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 36
4.2.1 Jitter Generation ................................................................................................................................ 37
Figure 28. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 37
5.0 Diagnostic Features ......................................................................................................................... 38
5.1 PRBS G
ENERATOR
AND
D
ETECTOR
................................................................................................................. 38
Figure 29. PRBS MODE ................................................................................................................................. 38
5.2 LOOPBACKS ................................................................................................................................................ 39
5.2.1 ANALOG LOOPBACK ........................................................................................................................ 39
Figure 30. Analog Loopback ........................................................................................................................... 39
5.2.2 DIGITAL LOOPBACK ......................................................................................................................... 40
5.2.3 REMOTE LOOPBACK ........................................................................................................................ 40
Figure 31. Digital Loopback ............................................................................................................................ 40
Figure 32. Remote Loopback ......................................................................................................................... 40
5.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 41
Figure 33. Transmit All Ones (TAOS) ............................................................................................................. 41
6.0 Microprocessor interface Block ..................................................................................................... 42
T
ABLE
11: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
...................................................................... 42
Figure 34. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 42
6.1 T
HE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
S
IGNALS
........................................................................................ 43
T
ABLE
12: XRT73L06 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
......................................................................... 43
6.2 A
SYNCHRONOUS
AND
S
YNCHRONOUS
D
ESCRIPTION
......................................................................................... 44
T
ABLE
13: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
......................................................................................... 45
Figure 35.
Asynchronous μP Interface Signals During Programmed I/O Read and Write Operations ........... 45
Figure 36. Synchronous μP Interface Signals During Programmed I/O Read and Write Operations ............ 46
T
ABLE
14: S
YNCHRONOUS
T
IMING
S
PECIFICATIONS
........................................................................................... 46
Figure 37. Interrupt process ........................................................................................................................... 47
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