參數(shù)資料
型號： XRT73L04BIV
廠商： Exar Corporation
文件頁數(shù)： 49/64頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 4CH 144LQFP
標(biāo)準(zhǔn)包裝： 60
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 4/4
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
49
b. Operating in the Hardware Mode.
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, pull both the LLB input pin and
the RLB input pin "High".
4.3
THE REMOTE LOOP-BACK MODE
When a given channel is configured to operate in the
Remote Loop-Back Mode, the channel ignores any
signals that are input to the TPData and TNData input
pins. The channel receives the incoming line signal
via the RTIP and RRing input pins. This data is pro-
cessed through the entire Receive Section and is out-
put to the Receive Terminal Equipment via the RPOS,
RNEG and RxClk output pins. Additionally, this data
is also internally looped back into the Pulse-Shaping
block within the Transmit Section. At this point, this
data is routed through the remainder of the Transmit
Section of the channel and transmitted out onto the
line via the TTIP_(n) and TRing_(n) output pins.
Figure 35 illustrates the path that the data takes when
the chip is configured to operate in the Remote Loop-
Back Mode.
Configure a channel to operate in the Remote Loop-
Back Mode by employing either one of the following
two steps
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Remote
Loop-Back Mode, write a "1" into the RLB bit-field,
and a "0" into the LLB bit-field, within Command Reg-
ister CR4.
b. Operating in the Hardware Mode
To configure Channel(n) to operate in the Remote
Loop-Back Mode, pull both the RLB_(n) input pin to
“High" and the LLB_(n) input pin to "Low".
FIGURE 35. THE REMOTE LOOP-BACK PATH, WITHIN A GIVEN CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS/(SR/DR)
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1, 2, or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_(n)
E3_(n)
LLB_(n)
RLB_(n)
XX
X
0
1
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