參數(shù)資料
型號: XRT73L03B
廠商: Exar Corporation
英文描述: 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
中文描述: 三通道DS3/E3/STS-1線路接口單元
文件頁數(shù): 4/61頁
文件大?。?/td> 342K
代理商: XRT73L03B
XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
F
EATURES
.................................................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
T
YPICAL
A
PPLICATIONS
................................................................................................................................. 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
: ..................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
: ....................................................................................................... 2
ORDERING INFORMATION ............................................................................................... 3
PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 7
O
PERATING
M
ODE
S
ELECT
........................................................................................................................... 7
C
ONTROL
AND
A
LARM
I
NTERFACE
................................................................................................................. 9
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................... 11
P
OWER
AND
G
ROUND
P
INS
......................................................................................................................... 13
N
O
C
ONNECTION
P
INS
................................................................................................................................ 14
ELECTRICAL CHARACTERISTICS ................................................................................ 15
A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................................................................... 15
SYSTEM DESCRIPTION .................................................................................................. 24
T
HE
T
RANSMIT
S
ECTION
- C
HANNELS
0, 1
AND
2 ......................................................................................... 24
T
HE
R
ECEIVE
S
ECTION
- C
HANNELS
0, 1
AND
2 ........................................................................................... 24
T
HE
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
................................................................................................. 24
1.0 Selecting the Data Rate .................................................................................................................... 25
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................................... 25
2.0 The Transmit Section ....................................................................................................................... 27
C
OMMAND
R
EGISTER
, CR4-(
N
) ...................................................................................................... 27
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
............................................................................................................................ 27
2.1.1 Accepting Dual-Rail Data from the Terminal Equipment ...................................................................... 27
2.1.2 Accepting Single-Rail Data from the Terminal Equipment ................................................................... 28
C
OMMAND
R
EGISTER
CR1-(
N
) ....................................................................................................... 28
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
................................................................................... 29
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
.................................................................................................................. 29
2.3.1 B3ZS Encoding .................................................................................................................................... 29
2.3.2 HDB3 Encoding .................................................................................................................................... 30
2.3.3 Disabling the HDB3/B3ZS Encoder ..................................................................................................... 30
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 30
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPING
C
IRCUITRY
....................................................................................................... 31
2.4.1 Enabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 32
2.4.2 Disabling the Transmit Line Build-Out Circuit ....................................................................................... 32
C
OMMAND
R
EGISTER
, CR1-(
N
) ...................................................................................................... 33
2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit ......................................................... 33
2.4.4 The Transmit Line Build-Out Circuit and E3 Applications .................................................................... 33
2.5 I
NTERFACING
THE
T
RANSMIT
S
ECTIONS
OF
THE
XRT73L03B
TO
THE
L
INE
......................................................... 33
T
RANSFORMER
R
ECOMMENDATIONS
............................................................................................... 34
3.0 The Receive Section ......................................................................................................................... 35
3.1 I
NTERFACING
THE
R
ECEIVE
S
ECTIONS
OF
THE
XRT73L03B
TO
THE
L
INE
........................................................... 35
3.2 T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
...................................................................................................................... 36
3.2.1 Guidelines for Setting the Receive Equalizer ...................................................................................... 36
C
OMMAND
R
EGISTER
CR2-(
N
) ....................................................................................................... 37
3.3 C
LOCK
R
ECOVERY
PLL .................................................................................................................................... 38
3.3.1 The Training Mode ............................................................................................................................... 38
3.3.2 The Data/Clock Recovery Mode .......................................................................................................... 38
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