TABLE 17: R
參數(shù)資料
型號: XRT73L02MIV-F
廠商: Exar Corporation
文件頁數(shù): 33/46頁
文件大?。?/td> 0K
描述: IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
xr
XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
37
TABLE 17: REGISTER MAP DESCRIPTION - CHANNEL 0
ADDRESS
(HEX)
TYPE
REGISTER
NAME
BIT#
SYMBOL
DESCRIPTION
DEFAULT
VALUE
0x01 (ch 0)
0x09 (ch 1)
R/W
Interrupt
Enable
(source
level)
D0
DMOIE_n
Writing a “1” to this bit enables an interrupt when the
no transmission detected on channel output.
0
D1
RLOSIE_n Writing a “1” to this bit enables an interrupt when
Receive Los of Signal is detected.
0
D2
RLOLIE_n
Writing a “1” to this bit enables an interrupt when
Receive Loss of Lock condition is detected
0
D3
Reserved
0
D7-D4
Reserved
0x02 (ch 0)
0x0A (ch 1)
Reset
on
Read
Interrupt
Status
(source
level)
D0
DMOIS_n
This bit is set every time a DMO status change has
occurred since the last cleared interrupt.This bit is
cleared when the register bit is read.
0
D1
RLOSIS_n This bit is set every time a RLOS status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D2
RLOLIS_n
This bit is set every time a RLOL status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D3
Reserved
0
D7-D4
Reserved
0x03 (ch 0)
0x0B (ch 1)
Read
Only
Alarm Sta-
tus
D0
DMO_n
This bit is set every time the MTIP_0/MRing_0 input
pins have not detected any bipolar pulses for 128
consecutive bit periods.
0
D1
RLOS_n
This bit is set every time the receiver declares an
LOS condition.
0
D2
RLOL_n
This bit is set every time when the receiver declares
a Loss of Lock condition.
0
D3
Reserved
0
D4
ALOS_n
This bit is set every time the receiver declares Ana-
log LOS condition.
0
D5
DLOS_n
This bit is set every time the receiver declares Digital
LOS condition.
0
D6
PRBSLS_n This bit is set every time the PRBS detector is not in
sync.
0
D7
Reserved
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